Lines Matching refs:BaseKill

106                   int Offset, unsigned Base, bool BaseKill, int Opcode,
118 bool BaseKill,
480 int Offset, unsigned Base, bool BaseKill, in MergeOps() argument
586 .addReg(Base, getKillRegState(BaseKill)); in MergeOps()
589 .addReg(Base, getKillRegState(BaseKill)) in MergeOps()
594 BaseKill = false; in MergeOps()
599 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset/4) in MergeOps()
603 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) in MergeOps()
607 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) in MergeOps()
611 BaseKill = true; // New base is always killed straight away. in MergeOps()
630 if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill) in MergeOps()
644 .addReg(Base, getKillRegState(BaseKill)); in MergeOps()
648 if (!BaseKill) in MergeOps()
654 MIB.addReg(Base, getKillRegState(BaseKill)); in MergeOps()
732 unsigned Base, bool BaseKill, in MergeOpsUpdate() argument
785 if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode, in MergeOpsUpdate()
847 bool BaseKill = false; in MergeLDR_STR() local
888 BaseKill = Loc->killsRegister(Base); in MergeLDR_STR()
891 BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
903 BaseKill = Loc->killsRegister(Base); in MergeLDR_STR()
905 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
1109 bool BaseKill = MI->getOperand(0).isKill(); in MergeBaseUpdateLSMultiple() local
1172 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
1249 bool BaseKill = MI->getOperand(1).isKill(); in MergeBaseUpdateLoadStore() local
1329 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1454 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR() argument
1462 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1468 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1501 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp() local
1517 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1524 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1547 (BaseKill || OffKill) && in FixInvalidRegPairOp()
1557 BaseReg, BaseKill, BaseUndef, OffKill, OffUndef, in FixInvalidRegPairOp()
1577 BaseReg, BaseKill, BaseUndef, OffKill, OffUndef, in FixInvalidRegPairOp()