Lines Matching refs:BaseReg
1454 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR() argument
1462 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1468 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1480 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1487 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3(); in FixInvalidRegPairOp()
1517 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1524 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1548 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1549 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1552 BaseReg, false, BaseUndef, false, OffUndef, in FixInvalidRegPairOp()
1557 BaseReg, BaseKill, BaseUndef, OffKill, OffUndef, in FixInvalidRegPairOp()
1568 if (EvenReg == BaseReg) in FixInvalidRegPairOp()
1572 BaseReg, false, BaseUndef, false, OffUndef, in FixInvalidRegPairOp()
1577 BaseReg, BaseKill, BaseUndef, OffKill, OffUndef, in FixInvalidRegPairOp()
1866 unsigned &OddReg, unsigned &BaseReg,
1962 unsigned &OddReg, unsigned &BaseReg, in CanFormLdStDWord() argument
2026 BaseReg = Op0->getOperand(1).getReg(); in CanFormLdStDWord()
2121 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
2128 EvenReg, OddReg, BaseReg, in RescheduleOps()
2143 .addReg(BaseReg); in RescheduleOps()
2157 .addReg(BaseReg); in RescheduleOps()