450         .addReg(Base, getKillRegState(false)).addImm(WordOffset * 4)  in UpdateBaseRegUses()
451         .addImm(Pred).addReg(PredReg);  in UpdateBaseRegUses()
469       .addReg(Base, getKillRegState(false)).addImm(WordOffset * 4)  in UpdateBaseRegUses()
470       .addImm(Pred).addReg(PredReg);  in UpdateBaseRegUses()
586             .addReg(Base, getKillRegState(BaseKill));  in MergeOps()
589             .addReg(Base, getKillRegState(BaseKill))  in MergeOps()
590             .addImm(Pred).addReg(PredReg);  in MergeOps()
599           .addReg(Base, getKillRegState(BaseKill)).addImm(Offset/4)  in MergeOps()
600           .addImm(Pred).addReg(PredReg);  in MergeOps()
603           .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)  in MergeOps()
604           .addImm(Pred).addReg(PredReg);  in MergeOps()
607         .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)  in MergeOps()
608         .addImm(Pred).addReg(PredReg).addReg(0);  in MergeOps()
643     MIB.addReg(Base, getDefRegState(true))  in MergeOps()
644        .addReg(Base, getKillRegState(BaseKill));  in MergeOps()
654     MIB.addReg(Base, getKillRegState(BaseKill));  in MergeOps()
657   MIB.addImm(Pred).addReg(PredReg);  in MergeOps()
660     MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)  in MergeOps()
665     MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);  in MergeOps()
1171     .addReg(Base, getDefRegState(true)) // WB base register  in MergeBaseUpdateLSMultiple()
1172     .addReg(Base, getKillRegState(BaseKill))  in MergeBaseUpdateLSMultiple()
1173     .addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSMultiple()
1328       .addReg(Base, getDefRegState(true)) // WB base register  in MergeBaseUpdateLoadStore()
1329       .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1330       .addImm(Pred).addReg(PredReg)  in MergeBaseUpdateLoadStore()
1331       .addReg(MO.getReg(), (isLd ? getDefRegState(true) :  in MergeBaseUpdateLoadStore()
1339           .addReg(Base, RegState::Define)  in MergeBaseUpdateLoadStore()
1340           .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1344           .addReg(Base, RegState::Define)  in MergeBaseUpdateLoadStore()
1345           .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1351         .addReg(Base, RegState::Define)  in MergeBaseUpdateLoadStore()
1352         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1363         .addReg(MO.getReg(), getKillRegState(MO.isKill()))  in MergeBaseUpdateLoadStore()
1364         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1369         .addReg(MO.getReg(), getKillRegState(MO.isKill()))  in MergeBaseUpdateLoadStore()
1370         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1461       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))  in InsertLDR_STR()
1462       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1463     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1467       .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))  in InsertLDR_STR()
1468       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1469     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1517           .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1518           .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1519           .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))  in FixInvalidRegPairOp()
1520           .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill));  in FixInvalidRegPairOp()
1524           .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1525           .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1526           .addReg(EvenReg,  in FixInvalidRegPairOp()
1528           .addReg(OddReg,  in FixInvalidRegPairOp()
2141               .addReg(EvenReg, RegState::Define)  in RescheduleOps()
2142               .addReg(OddReg, RegState::Define)  in RescheduleOps()
2143               .addReg(BaseReg);  in RescheduleOps()
2148               MIB.addReg(0);  in RescheduleOps()
2149             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2155               .addReg(EvenReg)  in RescheduleOps()
2156               .addReg(OddReg)  in RescheduleOps()
2157               .addReg(BaseReg);  in RescheduleOps()
2162               MIB.addReg(0);  in RescheduleOps()
2163             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()