Lines Matching refs:isThumb1
75 bool isThumb1, isThumb2; member
383 assert(isThumb1 && "Can only update base register uses for Thumb1!"); in UpdateBaseRegUses()
492 bool SafeToClobberCPSR = !isThumb1 || in MergeOps()
496 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback. in MergeOps()
501 if (isThumb1) in MergeOps()
516 bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1; in MergeOps()
522 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) { in MergeOps()
555 (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi : in MergeOps()
556 (isThumb1 && Offset < 8) ? ARM::tADDi3 : in MergeOps()
557 isThumb1 ? ARM::tADDi8 : ARM::ADDri; in MergeOps()
563 (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 : in MergeOps()
564 isThumb1 ? ARM::tSUBi8 : ARM::SUBri; in MergeOps()
571 if (isThumb1) { in MergeOps()
630 if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill) in MergeOps()
1105 if (isThumb1) return false; in MergeBaseUpdateLSMultiple()
1245 if (isThumb1) return false; in MergeBaseUpdateLoadStore()
1720 RS->FindUnusedReg(isThumb1 ? &ARM::tGPRRegClass : &ARM::GPRRegClass); in LoadStoreMultipleOpti()
1788 if (isThumb1) return false; in MergeReturnIntoLDM()
1825 isThumb1 = AFI->isThumbFunction() && !isThumb2; in runOnMachineFunction()