Lines Matching refs:ARM_AM
204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
491 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
501 ARM_AM::ShiftOpc ShiftTy;
511 ARM_AM::ShiftOpc ShiftTy;
518 ARM_AM::ShiftOpc ShiftTy;
783 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); in isFPImm()
1054 return (ARM_AM::getSOImmVal(Value) != -1 || in isAdrLabel()
1055 ARM_AM::getSOImmVal(-Value) != -1);; in isAdrLabel()
1062 return ARM_AM::getT2SOImmVal(Value) != -1; in isT2SOImm()
1069 return ARM_AM::getT2SOImmVal(Value) == -1 && in isT2SOImmNot()
1070 ARM_AM::getT2SOImmVal(~Value) != -1; in isT2SOImmNot()
1078 return ARM_AM::getT2SOImmVal(Value) == -1 && in isT2SOImmNeg()
1079 ARM_AM::getT2SOImmVal(-Value) != -1; in isT2SOImmNeg()
1106 return ARM_AM::getSOImmVal(~Value) != -1; in isModImmNot()
1113 return ARM_AM::getSOImmVal(Value) == -1 && in isModImmNeg()
1114 ARM_AM::getSOImmVal(-Value) != -1; in isModImmNeg()
1119 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1226 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1240 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1265 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1271 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1286 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1288 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1296 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1645 return ARM_AM::isNEONi16splat(Value); in isNEONi16splat()
1655 return ARM_AM::isNEONi16splat(~Value & 0xffff); in isNEONi16splatNot()
1667 return ARM_AM::isNEONi32splat(Value); in isNEONi32splat()
1677 return ARM_AM::isNEONi32splat(~Value); in isNEONi32splatNot()
1809 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1820 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
1864 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands()
1871 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands()
1906 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); in addFPImmOperands()
2122 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode2Operands()
2126 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2130 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, in addAddrMode2Operands()
2143 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM2OffsetImmOperands()
2147 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
2166 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode3Operands()
2170 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAddrMode3Operands()
2174 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); in addAddrMode3Operands()
2185 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2194 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM3OffsetOperands()
2198 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAM3OffsetOperands()
2216 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode5Operands()
2220 Val = ARM_AM::getAM5Opc(AddSub, Val); in addAddrMode5Operands()
2309 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, in addMemRegOffsetOperands()
2391 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
2392 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, in addPostIdxRegShiftedOperands()
2451 Value = ARM_AM::encodeNEONi16splat(Value); in addNEONi16splatOperands()
2460 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); in addNEONi16splatNotOperands()
2469 Value = ARM_AM::encodeNEONi32splat(Value); in addNEONi32splatOperands()
2478 Value = ARM_AM::encodeNEONi32splat(~Value); in addNEONi32splatNotOperands()
2619 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
2633 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
2765 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
2783 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
2890 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
2891 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " in print()
2914 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) in print()
2920 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) in print()
3056 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
3057 .Case("asl", ARM_AM::lsl) in tryParseShiftRegister()
3058 .Case("lsl", ARM_AM::lsl) in tryParseShiftRegister()
3059 .Case("lsr", ARM_AM::lsr) in tryParseShiftRegister()
3060 .Case("asr", ARM_AM::asr) in tryParseShiftRegister()
3061 .Case("ror", ARM_AM::ror) in tryParseShiftRegister()
3062 .Case("rrx", ARM_AM::rrx) in tryParseShiftRegister()
3063 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
3065 if (ShiftTy == ARM_AM::no_shift) in tryParseShiftRegister()
3082 if (ShiftTy == ARM_AM::rrx) { in tryParseShiftRegister()
3109 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || in tryParseShiftRegister()
3110 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
3117 ShiftTy = ARM_AM::lsl; in tryParseShiftRegister()
3133 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4430 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm()
4604 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg()
4686 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
4795 ARM_AM::no_shift, 0, 0, false, in parseMemory()
4852 ARM_AM::no_shift, 0, Align, in parseMemory()
4901 ARM_AM::no_shift, 0, 0, in parseMemory()
4930 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; in parseMemory()
4962 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, in parseMemRegOffsetShift()
4972 St = ARM_AM::lsl; in parseMemRegOffsetShift()
4974 St = ARM_AM::lsr; in parseMemRegOffsetShift()
4976 St = ARM_AM::asr; in parseMemRegOffsetShift()
4978 St = ARM_AM::ror; in parseMemRegOffsetShift()
4980 St = ARM_AM::rrx; in parseMemRegOffsetShift()
4987 if (St != ARM_AM::rrx) { in parseMemRegOffsetShift()
5007 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || in parseMemRegOffsetShift()
5008 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) in parseMemRegOffsetShift()
5012 St = ARM_AM::lsl; in parseMemRegOffsetShift()
5090 float RealVal = ARM_AM::getFPImmFloat(Val); in parseFPImm()
6748 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); in processInstruction()
7906 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { in processInstruction()
7908 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
7909 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
7910 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
7911 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
7940 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { in processInstruction()
7942 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
7943 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
7944 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
7945 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
7946 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
7948 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); in processInstruction()
7971 ARM_AM::ShiftOpc ShiftTy; in processInstruction()
7974 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
7975 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
7976 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
7977 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
7979 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); in processInstruction()
7996 ARM_AM::ShiftOpc ShiftTy; in processInstruction()
7999 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
8000 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
8001 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
8002 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
8008 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) in processInstruction()
8010 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); in processInstruction()
8024 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); in processInstruction()
8106 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
8115 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
8364 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); in processInstruction()
8366 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) in processInstruction()
8368 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { in processInstruction()
8389 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); in processInstruction()
8390 if (SOpc == ARM_AM::rrx) return false; in processInstruction()
8402 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && in processInstruction()
8403 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { in processInstruction()