465     unsigned RegNum;  member
470     unsigned RegNum;  member
499     unsigned RegNum;  member
677     return Reg.RegNum;  in getReg()
1444               .contains(VectorList.RegNum));  in isVecListDPair()
1461               .contains(VectorList.RegNum));  in isVecListDPairSpaced()
1488               .contains(VectorList.RegNum));  in isVecListDPairAllLanes()
1763     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;  in addCondCodeOperands()  local
1764     Inst.addOperand(MCOperand::CreateReg(RegNum));  in addCondCodeOperands()
2186       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));  in addAM3OffsetOperands()
2382     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));  in addPostIdxRegOperands()
2388     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));  in addPostIdxRegShiftedOperands()
2414     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));  in addVecListOperands()
2419     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));  in addVecListIndexedOperands()
2592   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {  in CreateCCOut()  argument
2594     Op->Reg.RegNum = RegNum;  in CreateCCOut()
2609   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,  in CreateReg()  argument
2612     Op->Reg.RegNum = RegNum;  in CreateReg()
2707   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,  in CreateVectorList()  argument
2712     Op->VectorList.RegNum = RegNum;  in CreateVectorList()
2721   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,  in CreateVectorListAllLanes()  argument
2724     Op->VectorList.RegNum = RegNum;  in CreateVectorListAllLanes()
2733   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,  in CreateVectorListIndexed()  argument
2736     Op->VectorList.RegNum = RegNum;  in CreateVectorListIndexed()
2783   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
2786     Op->PostIdxReg.RegNum = RegNum;  in CreatePostIdxReg()
2889        << PostIdxReg.RegNum;  in print()
2951        << VectorList.RegNum << ">";  in print()
2955        << VectorList.RegNum << ">";  in print()
2959        << VectorList.Count << " * " << VectorList.RegNum << ">";  in print()
2997   unsigned RegNum = MatchRegisterName(lowerCase);  in tryParseRegister()  local
2998   if (!RegNum) {  in tryParseRegister()
2999     RegNum = StringSwitch<unsigned>(lowerCase)  in tryParseRegister()
3022   if (!RegNum) {  in tryParseRegister()
3035   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)  in tryParseRegister()
3040   return RegNum;  in tryParseRegister()