Lines Matching refs:ShiftReg
513 unsigned ShiftReg; member
1807 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2620 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2625 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
2915 << " " << RegShiftedReg.ShiftReg << ">"; in print()
3081 int ShiftReg = 0; in tryParseShiftRegister() local
3086 ShiftReg = SrcReg; in tryParseShiftRegister()
3121 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3122 if (ShiftReg == -1) { in tryParseShiftRegister()
3133 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
3135 ShiftReg, Imm, in tryParseShiftRegister()