Lines Matching refs:ARM
37 NopInst.setOpcode(ARM::tHINT); in getNoopForMachoTarget()
79 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
140 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
141 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in storeRegToStackSlot()
142 RC == &ARM::GPRnopcRegClass) { in storeRegToStackSlot()
143 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
149 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
154 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
156 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
157 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
158 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
182 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in loadRegFromStackSlot()
183 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in loadRegFromStackSlot()
184 RC == &ARM::GPRnopcRegClass) { in loadRegFromStackSlot()
185 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
195 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
197 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot()
198 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
215 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12, RM); in expandLoadStackGuard()
217 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12, RM); in expandLoadStackGuard()
226 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
237 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
249 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) in emitT2RegPlusImmediate()
258 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) in emitT2RegPlusImmediate()
264 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) in emitT2RegPlusImmediate()
277 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
279 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg) in emitT2RegPlusImmediate()
281 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
286 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
288 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { in emitT2RegPlusImmediate()
290 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
298 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
310 assert(DestReg != ARM::SP && BaseReg != ARM::SP); in emitT2RegPlusImmediate()
311 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
315 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
344 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
345 case ARM::t2LDRHi12: return ARM::t2LDRHi8; in negativeOffsetOpcode()
346 case ARM::t2LDRBi12: return ARM::t2LDRBi8; in negativeOffsetOpcode()
347 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8; in negativeOffsetOpcode()
348 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8; in negativeOffsetOpcode()
349 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
350 case ARM::t2STRBi12: return ARM::t2STRBi8; in negativeOffsetOpcode()
351 case ARM::t2STRHi12: return ARM::t2STRHi8; in negativeOffsetOpcode()
352 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
354 case ARM::t2LDRi8: in negativeOffsetOpcode()
355 case ARM::t2LDRHi8: in negativeOffsetOpcode()
356 case ARM::t2LDRBi8: in negativeOffsetOpcode()
357 case ARM::t2LDRSHi8: in negativeOffsetOpcode()
358 case ARM::t2LDRSBi8: in negativeOffsetOpcode()
359 case ARM::t2STRi8: in negativeOffsetOpcode()
360 case ARM::t2STRBi8: in negativeOffsetOpcode()
361 case ARM::t2STRHi8: in negativeOffsetOpcode()
362 case ARM::t2PLDi8: in negativeOffsetOpcode()
376 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
377 case ARM::t2LDRHi8: return ARM::t2LDRHi12; in positiveOffsetOpcode()
378 case ARM::t2LDRBi8: return ARM::t2LDRBi12; in positiveOffsetOpcode()
379 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12; in positiveOffsetOpcode()
380 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12; in positiveOffsetOpcode()
381 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
382 case ARM::t2STRBi8: return ARM::t2STRBi12; in positiveOffsetOpcode()
383 case ARM::t2STRHi8: return ARM::t2STRHi12; in positiveOffsetOpcode()
384 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
386 case ARM::t2LDRi12: in positiveOffsetOpcode()
387 case ARM::t2LDRHi12: in positiveOffsetOpcode()
388 case ARM::t2LDRBi12: in positiveOffsetOpcode()
389 case ARM::t2LDRSHi12: in positiveOffsetOpcode()
390 case ARM::t2LDRSBi12: in positiveOffsetOpcode()
391 case ARM::t2STRi12: in positiveOffsetOpcode()
392 case ARM::t2STRBi12: in positiveOffsetOpcode()
393 case ARM::t2STRHi12: in positiveOffsetOpcode()
394 case ARM::t2PLDi12: in positiveOffsetOpcode()
408 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
409 case ARM::t2LDRHs: return ARM::t2LDRHi12; in immediateOffsetOpcode()
410 case ARM::t2LDRBs: return ARM::t2LDRBi12; in immediateOffsetOpcode()
411 case ARM::t2LDRSHs: return ARM::t2LDRSHi12; in immediateOffsetOpcode()
412 case ARM::t2LDRSBs: return ARM::t2LDRSBi12; in immediateOffsetOpcode()
413 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
414 case ARM::t2STRBs: return ARM::t2STRBi12; in immediateOffsetOpcode()
415 case ARM::t2STRHs: return ARM::t2STRHi12; in immediateOffsetOpcode()
416 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
418 case ARM::t2LDRi12: in immediateOffsetOpcode()
419 case ARM::t2LDRHi12: in immediateOffsetOpcode()
420 case ARM::t2LDRBi12: in immediateOffsetOpcode()
421 case ARM::t2LDRSHi12: in immediateOffsetOpcode()
422 case ARM::t2LDRSBi12: in immediateOffsetOpcode()
423 case ARM::t2STRi12: in immediateOffsetOpcode()
424 case ARM::t2STRBi12: in immediateOffsetOpcode()
425 case ARM::t2STRHi12: in immediateOffsetOpcode()
426 case ARM::t2PLDi12: in immediateOffsetOpcode()
427 case ARM::t2LDRi8: in immediateOffsetOpcode()
428 case ARM::t2LDRHi8: in immediateOffsetOpcode()
429 case ARM::t2LDRBi8: in immediateOffsetOpcode()
430 case ARM::t2LDRSHi8: in immediateOffsetOpcode()
431 case ARM::t2LDRSBi8: in immediateOffsetOpcode()
432 case ARM::t2STRi8: in immediateOffsetOpcode()
433 case ARM::t2STRBi8: in immediateOffsetOpcode()
434 case ARM::t2STRHi8: in immediateOffsetOpcode()
435 case ARM::t2PLDi8: in immediateOffsetOpcode()
454 if (Opcode == ARM::INLINEASM) in rewriteT2FrameIndex()
457 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { in rewriteT2FrameIndex()
463 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
473 bool HasCCOut = Opcode != ARM::t2ADDri12; in rewriteT2FrameIndex()
478 MI.setDesc(TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
480 MI.setDesc(TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
496 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
632 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) in getITInstrPredicate()