Lines Matching refs:DestReg
114 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
169 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
185 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
195 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
198 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
203 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
204 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
208 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); in loadRegFromStackSlot()
222 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
225 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
226 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
237 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
249 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) in emitT2RegPlusImmediate()
250 .addReg(DestReg) in emitT2RegPlusImmediate()
258 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) in emitT2RegPlusImmediate()
260 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
264 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) in emitT2RegPlusImmediate()
265 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
277 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
279 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg) in emitT2RegPlusImmediate()
288 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { in emitT2RegPlusImmediate()
291 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate()
310 assert(DestReg != ARM::SP && BaseReg != ARM::SP); in emitT2RegPlusImmediate()
330 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate()
336 BaseReg = DestReg; in emitT2RegPlusImmediate()