Lines Matching refs:PredR
156 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
160 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
161 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
766 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
779 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI))) in getReachingDefForPred()
789 if (RR.Reg == PredR) { in getReachingDefForPred()
878 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) { in predicateAt() argument
906 MB.addReg(PredR); in predicateAt()
932 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
941 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI))) in renameInRange()
977 unsigned PredR = MP.getReg(); in predicate() local
978 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
995 if (!I->modifiesRegister(PredR, 0)) in predicate()
1008 if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR)) in predicate()
1064 predicateAt(RD, DefI, PastDefIt, PredR, Cond); in predicate()
1066 predicateAt(RD, DefI, TfrIt, PredR, Cond); in predicate()
1071 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt); in predicate()