Lines Matching refs:VT
628 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, in getIndexedAddressParts() argument
635 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { in getIndexedAddressParts()
672 EVT VT; in getPostIndexedAddressParts() local
677 VT = LD->getMemoryVT(); in getPostIndexedAddressParts()
680 VT = ST->getMemoryVT(); in getPostIndexedAddressParts()
689 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()
692 int ShiftAmount = VT.getSizeInBits() / 16; in getPostIndexedAddressParts()
961 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) { in createSplat() argument
962 if (VT.getSimpleVT() == MVT::v4i8) in createSplat()
963 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val); in createSplat()
965 if (VT.getSimpleVT() == MVT::v4i16) in createSplat()
966 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val); in createSplat()
1001 EVT VT = Op.getValueType(); in LowerSETCC() local
1016 if (VT.isVector()) in LowerSETCC()
1062 EVT VT = Op.getValueType(); in LowerLOAD() local
1077 if (VT == MVT::v4i16) { in LowerLOAD()
1137 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result); in LowerLOAD()
1171 EVT VT = Op.getValueType(); in LowerRETURNADDR() local
1177 return DAG.getLoad(VT, dl, DAG.getEntryNode(), in LowerRETURNADDR()
1178 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), in LowerRETURNADDR()
1184 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); in LowerRETURNADDR()
1193 EVT VT = Op.getValueType(); in LowerFRAMEADDR() local
1197 TRI->getFrameRegister(), VT); in LowerFRAMEADDR()
1199 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, in LowerFRAMEADDR()
1231 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) { in promoteLdStType() argument
1232 if (VT != PromotedLdStVT) { in promoteLdStType()
1233 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); in promoteLdStType()
1234 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), in promoteLdStType()
1237 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); in promoteLdStType()
1238 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), in promoteLdStType()
1290 MVT::SimpleValueType VT = (MVT::SimpleValueType) i; in HexagonTargetLowering() local
1294 setOperationAction(ISD::SELECT, VT, Expand); in HexagonTargetLowering()
1295 setOperationAction(ISD::SDIV, VT, Expand); in HexagonTargetLowering()
1296 setOperationAction(ISD::SREM, VT, Expand); in HexagonTargetLowering()
1297 setOperationAction(ISD::UDIV, VT, Expand); in HexagonTargetLowering()
1298 setOperationAction(ISD::UREM, VT, Expand); in HexagonTargetLowering()
1299 setOperationAction(ISD::ROTL, VT, Expand); in HexagonTargetLowering()
1300 setOperationAction(ISD::ROTR, VT, Expand); in HexagonTargetLowering()
1301 setOperationAction(ISD::FDIV, VT, Expand); in HexagonTargetLowering()
1302 setOperationAction(ISD::FNEG, VT, Expand); in HexagonTargetLowering()
1303 setOperationAction(ISD::UMUL_LOHI, VT, Expand); in HexagonTargetLowering()
1304 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in HexagonTargetLowering()
1305 setOperationAction(ISD::UDIVREM, VT, Expand); in HexagonTargetLowering()
1306 setOperationAction(ISD::SDIVREM, VT, Expand); in HexagonTargetLowering()
1307 setOperationAction(ISD::FPOW, VT, Expand); in HexagonTargetLowering()
1308 setOperationAction(ISD::CTPOP, VT, Expand); in HexagonTargetLowering()
1309 setOperationAction(ISD::CTLZ, VT, Expand); in HexagonTargetLowering()
1310 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); in HexagonTargetLowering()
1311 setOperationAction(ISD::CTTZ, VT, Expand); in HexagonTargetLowering()
1312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in HexagonTargetLowering()
1317 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType) j, VT, Expand); in HexagonTargetLowering()
1322 setTruncStoreAction(VT, (MVT::SimpleValueType) TargetVT, Expand); in HexagonTargetLowering()
1324 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in HexagonTargetLowering()
1325 setOperationAction(ISD::ConstantPool, VT, Expand); in HexagonTargetLowering()
1326 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in HexagonTargetLowering()
1327 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); in HexagonTargetLowering()
1328 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in HexagonTargetLowering()
1329 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); in HexagonTargetLowering()
1330 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Expand); in HexagonTargetLowering()
1331 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Expand); in HexagonTargetLowering()
1332 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in HexagonTargetLowering()
1333 setOperationAction(ISD::SRA, VT, Custom); in HexagonTargetLowering()
1334 setOperationAction(ISD::SHL, VT, Custom); in HexagonTargetLowering()
1335 setOperationAction(ISD::SRL, VT, Custom); in HexagonTargetLowering()
1337 if (!isTypeLegal(VT)) in HexagonTargetLowering()
1340 setOperationAction(ISD::ADD, VT, Legal); in HexagonTargetLowering()
1341 setOperationAction(ISD::SUB, VT, Legal); in HexagonTargetLowering()
1342 setOperationAction(ISD::MUL, VT, Legal); in HexagonTargetLowering()
1344 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in HexagonTargetLowering()
1345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in HexagonTargetLowering()
1346 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in HexagonTargetLowering()
1347 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in HexagonTargetLowering()
1348 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in HexagonTargetLowering()
1349 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in HexagonTargetLowering()
1612 for (MVT VT : MVT::fp_valuetypes()) in HexagonTargetLowering() local
1613 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1616 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering() local
1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1618 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1619 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1721 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering() local
1722 setOperationAction(ISD::UADDO, VT, Expand); in HexagonTargetLowering()
1723 setOperationAction(ISD::SADDO, VT, Expand); in HexagonTargetLowering()
1724 setOperationAction(ISD::USUBO, VT, Expand); in HexagonTargetLowering()
1725 setOperationAction(ISD::SSUBO, VT, Expand); in HexagonTargetLowering()
1875 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT, in shouldExpandBuildVectorWithShuffles() argument
1879 EVT EltVT = VT.getVectorElementType(); in shouldExpandBuildVectorWithShuffles()
1884 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues); in shouldExpandBuildVectorWithShuffles()
1894 EVT VT = Op.getValueType(); in LowerVECTOR_SHUFFLE() local
1905 return createSplat(DAG, dl, VT, V1.getOperand(0)); in LowerVECTOR_SHUFFLE()
1919 return createSplat(DAG, dl, VT, V1.getOperand(0)); in LowerVECTOR_SHUFFLE()
1921 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, MVT::i32)); in LowerVECTOR_SHUFFLE()
1955 EVT VT = Op.getValueType(); in LowerVECTOR_SHIFT() local
1969 if (VT.getSimpleVT() == MVT::v4i16) { in LowerVECTOR_SHIFT()
1972 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat); in LowerVECTOR_SHIFT()
1975 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat); in LowerVECTOR_SHIFT()
1978 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat); in LowerVECTOR_SHIFT()
1983 } else if (VT.getSimpleVT() == MVT::v2i32) { in LowerVECTOR_SHIFT()
1986 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat); in LowerVECTOR_SHIFT()
1989 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat); in LowerVECTOR_SHIFT()
1992 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat); in LowerVECTOR_SHIFT()
2001 return DAG.getNode(ISD::BITCAST, dl, VT, Result); in LowerVECTOR_SHIFT()
2008 EVT VT = Op.getValueType(); in LowerBUILD_VECTOR() local
2010 unsigned Size = VT.getSizeInBits(); in LowerBUILD_VECTOR()
2023 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) && in LowerBUILD_VECTOR()
2029 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, MVT::i32)); in LowerBUILD_VECTOR()
2033 if (VT.getSimpleVT() == MVT::v2i32) { in LowerBUILD_VECTOR()
2047 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0); in LowerBUILD_VECTOR()
2053 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0); in LowerBUILD_VECTOR()
2057 if (VT.getSimpleVT() == MVT::v2i16) { in LowerBUILD_VECTOR()
2108 EVT EltVT = VT.getVectorElementType(); in LowerBUILD_VECTOR()
2122 if (VT.getSizeInBits() == 64 && in LowerBUILD_VECTOR()
2125 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand); in LowerBUILD_VECTOR()
2133 if (VT.getSizeInBits() == 32) in LowerBUILD_VECTOR()
2140 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal); in LowerBUILD_VECTOR()
2147 EVT VT = Op.getValueType(); in LowerCONCAT_VECTORS() local
2163 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec); in LowerCONCAT_VECTORS()
2164 return DAG.getNode(ISD::BITCAST, dl, VT, Combined); in LowerCONCAT_VECTORS()
2172 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec); in LowerCONCAT_VECTORS()
2173 return DAG.getNode(ISD::BITCAST, dl, VT, Combined); in LowerCONCAT_VECTORS()
2181 if (VT.getSizeInBits() == 64 && in LowerCONCAT_VECTORS()
2184 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand); in LowerCONCAT_VECTORS()
2192 if (VT.getSizeInBits() == 32) in LowerCONCAT_VECTORS()
2198 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal); in LowerCONCAT_VECTORS()
2204 EVT VT = Op.getValueType(); in LowerEXTRACT_VECTOR() local
2205 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1; in LowerEXTRACT_VECTOR()
2261 if (VT.getSizeInBits() == 32) in LowerEXTRACT_VECTOR()
2265 return DAG.getNode(ISD::BITCAST, dl, VT, N); in LowerEXTRACT_VECTOR()
2282 if (VT.getSizeInBits() == 32) in LowerEXTRACT_VECTOR()
2285 return DAG.getNode(ISD::BITCAST, dl, VT, N); in LowerEXTRACT_VECTOR()
2291 EVT VT = Op.getValueType(); in LowerINSERT_VECTOR() local
2292 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1; in LowerINSERT_VECTOR()
2308 if (VT.getSizeInBits() == 32) in LowerINSERT_VECTOR()
2313 return DAG.getNode(ISD::BITCAST, dl, VT, N); in LowerINSERT_VECTOR()
2323 if (VT.getSizeInBits() == 64 && in LowerINSERT_VECTOR()
2326 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val); in LowerINSERT_VECTOR()
2332 if (VT.getSizeInBits() == 32) in LowerINSERT_VECTOR()
2337 return DAG.getNode(ISD::BITCAST, dl, VT, N); in LowerINSERT_VECTOR()
2450 MVT VT) const { in getRegForInlineAsmConstraint()
2454 switch (VT.SimpleTy) { in getRegForInlineAsmConstraint()
2471 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); in getRegForInlineAsmConstraint()
2477 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()