Lines Matching refs:IntRegs
164 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
193 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
195 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
196 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
198 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
199 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
201 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
202 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
204 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
209 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
244 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
272 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
273 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
274 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
275 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
278 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
279 (i32 IntRegs:$src1))), 0)))),
280 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
310 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
314 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
320 def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
321 (A4_combineri IntRegs:$r, s32ImmPred:$i)>;
323 def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
324 (A4_combineir s32ImmPred:$i, IntRegs:$r)>;
372 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
373 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
374 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
375 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
388 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
396 LDInst<(outs RC:$dst1, IntRegs:$dst2),
416 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
417 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
421 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
422 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
423 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
424 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
428 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
449 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
472 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
473 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
479 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
480 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
481 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
482 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
488 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
498 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
500 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
504 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
525 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
552 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
602 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
603 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
607 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
608 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
612 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
621 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
622 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
623 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
639 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
640 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
658 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
659 (Zext64 IntRegs:$src1)>;
676 : STInst<(outs IntRegs:$dst),
696 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
697 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
699 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
702 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
712 : NVInst <(outs IntRegs:$dst),
713 (ins u6Ext:$addr, IntRegs:$src),
743 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
767 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
768 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
770 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
772 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
780 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
782 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
785 (add (shl IntRegs:$src1, u2ImmPred:$src2),
787 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
790 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
791 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
795 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
796 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
797 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
804 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
836 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
864 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
898 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
925 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
994 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
995 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
998 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
999 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1002 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1003 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1009 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1013 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1014 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1015 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1041 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1070 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1236 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1272 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1333 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1337 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1341 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1350 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1356 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1357 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1386 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1387 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1420 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1421 (ins PredRegs:$src1, IntRegs:$src2,
1422 ImmOp:$offset, IntRegs:$src3),
1486 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1487 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1540 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1615 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1673 (ins IntRegs:$src1, brtarget:$offset),
1725 (ins IntRegs:$Rs),
1744 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1846 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1847 (L2_loadri_io IntRegs:$src1, s30_2ImmPred:$src2)>;
1871 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1888 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1889 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1891 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1892 (add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))],
1912 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1913 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1933 def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
1934 (i32 IntRegs:$src3))),
1935 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1938 def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
1939 (i32 IntRegs:$src3)),
1940 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1943 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1945 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1965 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
2015 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2039 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2061 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2094 ALU64Inst<(outs IntRegs:$Rx),
2095 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2097 [(set (i32 IntRegs:$Rx),
2098 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
2116 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2132 (ins IntRegs:$Rs, IntRegs:$Rt),
2148 (ins IntRegs:$Rs, IntRegs:$Rt),
2163 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2164 (ins IntRegs:$Rs, IntRegs:$Rt),
2179 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2180 (ins IntRegs:$Rs, IntRegs:$Rt),
2227 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2228 (not IntRegs:$src3)))),
2229 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2239 : MInst_acc <(outs IntRegs:$Rx),
2240 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2242 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2243 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
2320 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2335 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2355 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2356 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2357 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2358 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2365 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2366 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2369 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2370 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2400 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2401 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2403 [(set (i32 IntRegs:$Rd),
2404 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2426 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2427 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2429 [(set (i32 IntRegs:$Rd),
2430 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
2450 : ALU64Inst <(outs IntRegs:$dst), ins,
2453 [(set (i32 IntRegs:$dst),
2454 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2476 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2481 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2485 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2486 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2488 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2489 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2611 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2613 [(set (i32 IntRegs:$Rd),
2652 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2654 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2656 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2658 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2668 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2669 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2674 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2710 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2749 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2751 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2752 (i32 IntRegs:$Rt)))],
2852 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2883 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2952 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2953 IntRegs:$addr),
2954 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2957 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
2959 (add IntRegs:$base, ImmPred:$offset)),
2960 (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
2999 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3000 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3003 def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
3005 (add IntRegs:$base, ImmPred:$offset)),
3006 (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
3040 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3042 (add IntRegs:$base, extPred:$offset)),
3043 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3047 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3048 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3092 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3093 IntRegs:$addr),
3094 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3098 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3099 (i32 IntRegs:$orend)),
3100 (add IntRegs:$base, extPred:$offset)),
3101 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3161 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
3162 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
3163 // (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
3166 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
3167 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
3170 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
3171 (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
3197 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3199 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3387 : NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
3418 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3486 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3490 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3494 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3501 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3527 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3548 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3687 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3688 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3692 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3693 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3697 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3717 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3718 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3722 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3723 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3727 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3827 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3829 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>;
3887 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3888 IntRegs:$c, IntRegs:$d),
3891 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3893 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3894 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3896 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3944 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3950 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3976 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
3978 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
3999 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4045 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4099 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4154 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4207 (outs IntRegs:$Rd),
4227 (outs IntRegs:$Rd),
4228 (ins IntRegs:$Rs, brtarget:$r9_2),