Lines Matching refs:b11
145 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
1784 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1788 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1960 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1977 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1978 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
2029 let Inst{7-6} = 0b11;
2307 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2648 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2664 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2668 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2669 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2674 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2763 let Inst{7-6} = 0b11;
2914 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2922 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
3498 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3545 u16_3Imm, 0b11>, PredNewRel;
4016 let Inst{24-23} = 0b11;
4021 let Inst{9-8} = 0b11;
4172 let Inst{24-23} = 0b11;