Lines Matching refs:mnemonic
127 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
129 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
130 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
163 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
165 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
168 let CextOpcode = mnemonic;
207 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
210 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
213 let CextOpcode = mnemonic;
243 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
245 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
395 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
398 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
447 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
450 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
524 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
526 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
549 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
554 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
584 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
589 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
592 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
593 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
596 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
597 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
674 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
678 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
710 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
714 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
740 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
744 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
801 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
805 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
835 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
837 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
861 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
867 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
897 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
899 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
923 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
927 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
957 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
960 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
963 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
964 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
967 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
968 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
977 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
980 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
983 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
984 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
987 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
988 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1040 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1042 mnemonic#"($Rs+#$offset)=#$S8",
1067 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1072 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1109 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1111 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1113 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1116 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1119 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1121 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1122 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1233 class T_store_io_nv <string mnemonic, RegisterClass RC,
1237 mnemonic#"($src1+#$src2) = $src3.new",
1244 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1245 !if (!eq(mnemonic, "memh"), 12,
1246 !if (!eq(mnemonic, "memw"), 13, 0)));
1248 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1249 !if (!eq(mnemonic, "memh"), 1,
1250 !if (!eq(mnemonic, "memw"), 2, 0)));
1252 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1253 !if (!eq(mnemonic, "memh"), src2{11-1},
1254 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1269 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1274 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1284 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1285 !if (!eq(mnemonic, "memh"), 7,
1286 !if (!eq(mnemonic, "memw"), 8, 0)));
1288 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1289 !if (!eq(mnemonic, "memh"), 1,
1290 !if (!eq(mnemonic, "memw"), 2, 0)));
1292 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1293 !if (!eq(mnemonic, "memh"), src3{6-1},
1294 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1315 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1319 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1321 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1322 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1324 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1326 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1355 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1358 "$dst = "#mnemonic#"($src2++$src3)", [],
1385 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1388 mnemonic#"($src1++#$offset) = $src2.new",
1418 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1424 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1453 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1455 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1458 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1461 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1464 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1467 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1468 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1485 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1488 #mnemonic#"($src1++$src2) = $src3.new",
1537 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1541 "if ("#!if(isNegCond, "!","")#mnemonic#
1571 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1574 def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1576 def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1582 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1585 defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1586 defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1612 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1616 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1638 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1640 def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1642 def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
1645 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1647 defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1648 defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1670 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1674 "if ("#!if(isNegCond, "!","")#mnemonic
1694 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1697 def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1699 def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1702 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1705 defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1706 defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
2238 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2241 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2634 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2636 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2637 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2684 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2687 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2708 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2711 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
3210 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3213 !if(isPredNew, ".new) ", ") ")#mnemonic#
3235 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3237 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3238 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3239 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3243 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3245 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3253 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3254 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3282 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3285 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3314 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3318 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3344 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3346 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1, isHalf>,
3364 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3368 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3371 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3372 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3375 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3376 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3386 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3388 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3417 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3420 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3447 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3448 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3466 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3470 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3473 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3474 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3477 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3478 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3511 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3513 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3521 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3527 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3530 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3589 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3592 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3615 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3617 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1>, AddrModeRel {
3636 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3640 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3666 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3668 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3670 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3674 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3678 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3681 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3682 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3710 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3712 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {