Lines Matching refs:Instructions
177 SmallVectorImpl<MCInst> &Instructions);
180 SmallVectorImpl<MCInst> &Instructions);
183 SmallVectorImpl<MCInst> &Instructions);
186 SmallVectorImpl<MCInst> &Instructions);
189 SmallVectorImpl<MCInst> &Instructions);
191 SmallVectorImpl<MCInst> &Instructions);
194 SmallVectorImpl<MCInst> &Instructions);
197 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
201 SmallVectorImpl<MCInst> &Instructions);
204 SmallVectorImpl<MCInst> &Instructions);
282 SmallVectorImpl<MCInst> &Instructions);
1235 SmallVectorImpl<MCInst> &Instructions) { in processInstruction() argument
1387 Instructions.push_back(Inst); in processInstruction()
1388 createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions); in processInstruction()
1404 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true); in processInstruction()
1414 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); in processInstruction()
1418 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); in processInstruction()
1448 Instructions.push_back(TmpInst); in processInstruction()
1582 return expandInstruction(Inst, IDLoc, Instructions); in processInstruction()
1584 Instructions.push_back(Inst); in processInstruction()
1608 SmallVectorImpl<MCInst> &Instructions) { in expandInstruction() argument
1612 return expandLoadImm(Inst, IDLoc, Instructions); in expandInstruction()
1618 return expandLoadImm(Inst, IDLoc, Instructions); in expandInstruction()
1620 return expandLoadAddressImm(Inst, IDLoc, Instructions); in expandInstruction()
1622 return expandLoadAddressReg(Inst, IDLoc, Instructions); in expandInstruction()
1624 return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions); in expandInstruction()
1627 return expandLoadStoreMultiple(Inst, IDLoc, Instructions); in expandInstruction()
1630 return expandJalWithRegs(Inst, IDLoc, Instructions); in expandInstruction()
1637 SmallVectorImpl<MCInst> &Instructions) { in createShiftOr() argument
1645 Instructions.push_back(tmpInst); in createShiftOr()
1653 Instructions.push_back(tmpInst); in createShiftOr()
1658 SmallVectorImpl<MCInst> &Instructions) { in createShiftOr() argument
1661 IDLoc, Instructions); in createShiftOr()
1666 SmallVectorImpl<MCInst> &Instructions) { in expandJalWithRegs() argument
1690 Instructions.push_back(JalrInst); in expandJalWithRegs()
1701 Instructions.push_back(NopInst); in expandJalWithRegs()
1708 SmallVectorImpl<MCInst> &Instructions) { in expandLoadImm() argument
1726 Instructions.push_back(tmpInst); in expandLoadImm()
1734 Instructions.push_back(tmpInst); in expandLoadImm()
1742 Instructions.push_back(tmpInst); in expandLoadImm()
1743 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1767 Instructions.push_back(tmpInst); in expandLoadImm()
1768 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1769 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1794 Instructions.push_back(tmpInst); in expandLoadImm()
1795 createShiftOr<32, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1796 createShiftOr<16, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1797 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1804 SmallVectorImpl<MCInst> &Instructions) { in expandLoadAddressReg() argument
1810 expandLoadAddressSym(Inst, IDLoc, Instructions); in expandLoadAddressReg()
1825 Instructions.push_back(tmpInst); in expandLoadAddressReg()
1834 Instructions.push_back(tmpInst); in expandLoadAddressReg()
1840 Instructions.push_back(tmpInst); in expandLoadAddressReg()
1846 Instructions.push_back(tmpInst); in expandLoadAddressReg()
1853 SmallVectorImpl<MCInst> &Instructions) { in expandLoadAddressImm() argument
1859 expandLoadAddressSym(Inst, IDLoc, Instructions); in expandLoadAddressImm()
1872 Instructions.push_back(tmpInst); in expandLoadAddressImm()
1880 Instructions.push_back(tmpInst); in expandLoadAddressImm()
1886 Instructions.push_back(tmpInst); in expandLoadAddressImm()
1893 SmallVectorImpl<MCInst> &Instructions) { in expandLoadAddressSym() argument
1934 Instructions.push_back(tmpInst); in expandLoadAddressSym()
1937 Instructions); in expandLoadAddressSym()
1939 Instructions); in expandLoadAddressSym()
1941 Instructions); in expandLoadAddressSym()
1949 Instructions.push_back(tmpInst); in expandLoadAddressSym()
1952 Instructions); in expandLoadAddressSym()
1957 MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { in expandUncondBranchMMPseudo() argument
1986 Instructions.push_back(Inst); in expandUncondBranchMMPseudo()
1990 createNop(true, IDLoc, Instructions); in expandUncondBranchMMPseudo()
1996 SmallVectorImpl<MCInst> &Instructions, in expandMemInst() argument
2077 Instructions.push_back(TempInst); in expandMemInst()
2086 Instructions.push_back(TempInst); in expandMemInst()
2107 Instructions.push_back(TempInst); in expandMemInst()
2113 SmallVectorImpl<MCInst> &Instructions) { in expandLoadStoreMultiple() argument
2130 Instructions.push_back(Inst); in expandLoadStoreMultiple()
2135 SmallVectorImpl<MCInst> &Instructions) { in createNop() argument
2147 Instructions.push_back(NopInst); in createNop()
2169 SmallVector<MCInst, 8> Instructions; in MatchAndEmitInstruction() local
2175 if (processInstruction(Inst, IDLoc, Instructions)) in MatchAndEmitInstruction()
2177 for (unsigned i = 0; i < Instructions.size(); i++) in MatchAndEmitInstruction()
2178 Out.EmitInstruction(Instructions[i], STI); in MatchAndEmitInstruction()