Lines Matching refs:RO

167                       RegisterOperand RO> :
168   InstSE<(outs), (ins RO:$rs, opnd:$offset),
177 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
179   InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
181          [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
187 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
189   InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
191          [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
210 class MovePMM16<string opstr, RegisterOperand RO> :
211 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
247 class LLBaseMM<string opstr, RegisterOperand RO> :
248   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
254 class SCBaseMM<string opstr, RegisterOperand RO> :
255   InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
262 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
264   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
266          [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
272 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
275   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
277                   [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
281 class AndImmMM16<string opstr, RegisterOperand RO,
283   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
286 class LogicRMM16<string opstr, RegisterOperand RO,
289   MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
291          [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
296 class NotMM16<string opstr, RegisterOperand RO> :
297   MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
299          [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
301 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
303   MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
306 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
308   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
315 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
324 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
326   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
333 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
335   MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
341 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
343   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
350 class AddImmUR2<string opstr, RegisterOperand RO> :
351   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
357 class AddImmUS5<string opstr, RegisterOperand RO> :
358   MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
363 class AddImmUR1SP<string opstr, RegisterOperand RO> :
364   MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
371 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
372       MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
378 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
380   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
386 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
387   MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
393 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
394   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
395            [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
402 class JumpRegMM16<string opstr, RegisterOperand RO> :
403   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
421 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
422   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
430 class JumpRegCMM16<string opstr, RegisterOperand RO> :
431   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
445 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
446   MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
462   class JumpLinkRegMM<string opstr, RegisterOperand RO>:
463     InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
467                                   RegisterOperand RO> :
468     InstSE<(outs), (ins RO:$rs, opnd:$offset),
472 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
475   InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
478 class AddImmUPC<string opstr, RegisterOperand RO> :
479   InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),