Lines Matching refs:opstr
166 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
169 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
177 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
180 !strconcat(opstr, "\t$rt, $addr"),
187 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
190 !strconcat(opstr, "\t$rt, $addr"),
210 class MovePMM16<string opstr, RegisterOperand RO> :
212 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
231 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
234 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
239 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
242 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
247 class LLBaseMM<string opstr, RegisterOperand RO> :
249 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
254 class SCBaseMM<string opstr, RegisterOperand RO> :
256 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
262 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
265 !strconcat(opstr, "\t$rt, $addr"),
272 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
276 !strconcat(opstr, "\t$rd, $rs, $rt"),
281 class AndImmMM16<string opstr, RegisterOperand RO,
284 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
286 class LogicRMM16<string opstr, RegisterOperand RO,
290 !strconcat(opstr, "\t$rt, $rs"),
296 class NotMM16<string opstr, RegisterOperand RO> :
298 !strconcat(opstr, "\t$rt, $rs"),
301 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
304 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
306 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
309 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
315 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
319 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
324 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
327 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
333 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
336 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
341 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
344 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
350 class AddImmUR2<string opstr, RegisterOperand RO> :
352 !strconcat(opstr, "\t$rd, $rs, $imm"),
357 class AddImmUS5<string opstr, RegisterOperand RO> :
359 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
363 class AddImmUR1SP<string opstr, RegisterOperand RO> :
365 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
367 class AddImmUSP<string opstr> :
369 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
371 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
372 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
378 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
381 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
386 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
388 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
393 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
394 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
402 class JumpRegMM16<string opstr, RegisterOperand RO> :
403 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
421 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
422 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
430 class JumpRegCMM16<string opstr, RegisterOperand RO> :
431 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
440 class BrkSdbbp16MM<string opstr> :
442 !strconcat(opstr, "\t$code_"),
445 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
447 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
456 class JumpLinkMM<string opstr, DAGOperand opnd> :
457 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
458 [], IIBranch, FrmJ, opstr> {
462 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
463 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
466 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
469 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
472 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
476 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
478 class AddImmUPC<string opstr, RegisterOperand RO> :
480 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
509 class StoreMultMM<string opstr,
512 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
517 class LoadMultMM<string opstr,
520 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
525 class StoreMultMM16<string opstr,
529 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
534 class LoadMultMM16<string opstr,
538 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
543 class UncondBranchMM16<string opstr> :
545 !strconcat(opstr, "\t$offset"),
613 class WaitMM<string opstr> :
614 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
615 NoItinerary, FrmOther, opstr>;
927 class UncondBranchMMPseudo<string opstr> :
929 !strconcat(opstr, "\t$offset")>;