Lines Matching refs:rx
69 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
74 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
78 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
79 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
83 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
88 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
92 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
93 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
94 let Constraints = "$rx_ = $rx";
99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
100 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
108 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
109 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
168 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
169 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
180 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
185 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
189 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
194 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
197 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
201 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
202 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
206 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
207 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
211 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
212 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
213 let Constraints = "$rx_ = $rx";
221 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
222 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
226 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
227 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
257 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
258 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
266 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
278 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
308 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309 !strconcat(asmstr, "\t$rx, $ry"), []>;
315 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
325 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
326 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
335 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
336 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
340 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
341 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
347 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
348 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
351 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
357 FRR16<f, (outs CPU16Regs:$rx), (ins),
358 !strconcat(asmstr, "\t$rx"), [], itin>;
362 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
365 let Constraints = "$rx = $rz";
368 let rx=0 in
377 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
378 !strconcat(asmstr, "\t $rx"), [], itin> ;
383 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
384 !strconcat(asmstr, "\t $rx"),
386 let Constraints = "$rx_ = $rx";
393 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
394 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
492 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
493 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
529 // Format: ADDIU rx, immediate MIPS16e
549 // Format: ADDIU rx, pc, immediate MIPS16e
574 // Format: ADDU rz, rx, ry MIPS16e
582 // Format: AND rx, ry MIPS16e
590 // Format: BEQZ rx, offset MIPS16e
598 // Format: BEQZ rx, offset MIPS16e
619 // Format: BNEZ rx, offset MIPS16e
626 // Format: BNEZ rx, offset MIPS16e
694 // Format: CMP rx, ry MIPS16e
703 // Format: CMPI rx, immediate MIPS16e
712 // Format: CMPI rx, immediate MIPS16e
722 // Format: DIV rx, ry MIPS16e
731 // Format: DIVU rx, ry MIPS16e
786 // Format: LB ry, offset(rx) MIPS16e
795 // Format: LBU ry, offset(rx) MIPS16e
805 // Format: LH ry, offset(rx) MIPS16e
814 // Format: LHU ry, offset(rx) MIPS16e
824 // Format: LI rx, immediate MIPS16e
831 // Format: LI rx, immediate MIPS16e
842 // Format: LW ry, offset(rx) MIPS16e
850 // Format: LW rx, offset(sp) MIPS16e
876 // Format: MFHI rx MIPS16e
886 // Format: MFLO rx MIPS16e
911 // Format: MULT rx, ry MIPS16e
922 // Format: MULTU rx, ry MIPS16e
933 // Format: NEG rx, ry MIPS16e
940 // Format: NOT rx, ry MIPS16e
947 // Format: OR rx, ry MIPS16e
1002 // Format: SB ry, offset(rx) MIPS16e
1010 // Format: SEB rx MIPS16e
1012 // Sign-extend least significant byte in register rx.
1018 // Format: SEH rx MIPS16e
1020 // Sign-extend least significant word in register rx.
1140 // Format: SH ry, offset(rx) MIPS16e
1148 // Format: SLL rx, ry, sa MIPS16e
1155 // Format: SLLV ry, rx MIPS16e
1161 // Format: SLTI rx, immediate MIPS16e
1171 // Format: SLTI rx, immediate MIPS16e
1182 // Format: SLTIU rx, immediate MIPS16e
1192 // Format: SLTI rx, immediate MIPS16e
1201 // Format: SLTIU rx, immediate MIPS16e
1208 // Format: SLT rx, ry MIPS16e
1218 // Format: SLTU rx, ry MIPS16e
1234 // Format: SRAV ry, rx MIPS16e
1243 // Format: SRA rx, ry, sa MIPS16e
1252 // Format: SRLV ry, rx MIPS16e
1261 // Format: SRL rx, ry, sa MIPS16e
1269 // Format: SUBU rz, rx, ry MIPS16e
1276 // Format: SW ry, offset(rx) MIPS16e
1284 // Format: SW rx, offset(sp) MIPS16e
1285 // Purpose: Store Word rx (SP-Relative)
1293 // Format: XOR rx, ry MIPS16e
1396 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1397 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1400 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1401 (I CPU16Regs:$rx, imm_type:$imm16)>;
1438 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1439 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1444 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1445 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1449 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1450 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1457 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1458 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1465 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1466 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1472 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1473 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1480 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1481 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1485 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1486 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1493 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1494 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1501 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1502 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1506 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1507 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1511 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1512 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1519 <(brcond CPU16Regs:$rx, bb:$targ16),
1520 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1529 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1530 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1537 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1538 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1546 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1547 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1562 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1563 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1569 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1570 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;