Lines Matching refs:addReg
151 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
155 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
251 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
274 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
277 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
286 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
301 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
309 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
327 .addReg(MFI->getGlobalBaseReg()) in materializeGV()
333 .addReg(DestReg) in materializeGV()
511 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
512 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
517 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
518 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
522 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
526 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
531 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
532 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
537 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
538 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
542 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
546 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
551 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
552 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
557 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
558 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
604 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
605 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
606 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( in emitCmp()
609 .addReg(RegWithOne) in emitCmp()
610 .addReg(Mips::FCC0) in emitCmp()
611 .addReg(RegWithZero, RegState::Implicit); in emitCmp()
722 .addReg(SrcReg) in emitStore()
831 .addReg(CondReg) in selectBranch()
867 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
891 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
935 emitInst(Opc, TempReg).addReg(SrcReg); in selectFPToInt()
937 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1030 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1096 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1159 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1162 Mips::RA).addReg(Mips::T9); in fastLowerCall()
1166 MIB.addReg(Reg, RegState::Implicit); in fastLowerCall()
1253 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg); in selectRet()
1260 MIB.addReg(RetRegs[i], RegState::Implicit); in selectRet()
1328 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1329 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1339 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1342 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1363 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1); in emitIntZExt()
1366 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff); in emitIntZExt()
1369 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff); in emitIntZExt()
1447 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()