Lines Matching refs:addReg
232 MIB.addReg(MO.getReg()); in replaceBranch()
297 .addReg(Mips::SP).addImm(-8); in expandToLongBranch()
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
299 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
322 .addReg(Mips::AT) in expandToLongBranch()
329 .addReg(Mips::RA).addReg(Mips::AT); in expandToLongBranch()
331 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
335 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) in expandToLongBranch()
337 .addReg(Mips::SP).addImm(8)); in expandToLongBranch()
341 .addReg(Mips::SP).addImm(8); in expandToLongBranch()
344 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) in expandToLongBranch()
384 .addReg(Mips::SP_64).addImm(-16); in expandToLongBranch()
385 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64) in expandToLongBranch()
386 .addReg(Mips::SP_64).addImm(0); in expandToLongBranch()
388 Mips::AT_64).addReg(Mips::ZERO_64) in expandToLongBranch()
391 .addReg(Mips::AT_64).addImm(16); in expandToLongBranch()
397 .addReg(Mips::AT_64) in expandToLongBranch()
404 .addReg(Mips::RA_64).addReg(Mips::AT_64); in expandToLongBranch()
406 .addReg(Mips::SP_64).addImm(0); in expandToLongBranch()
409 .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64)) in expandToLongBranch()
411 .addReg(Mips::SP_64).addImm(16)); in expandToLongBranch()
447 .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); in emitGPDisp()