52         setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);  in MipsSETargetLowering()
53         setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);  in MipsSETargetLowering()
54         setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);  in MipsSETargetLowering()
66       for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)  in MipsSETargetLowering()
69       setOperationAction(ISD::ADD, VecTys[i], Legal);  in MipsSETargetLowering()
70       setOperationAction(ISD::SUB, VecTys[i], Legal);  in MipsSETargetLowering()
71       setOperationAction(ISD::LOAD, VecTys[i], Legal);  in MipsSETargetLowering()
72       setOperationAction(ISD::STORE, VecTys[i], Legal);  in MipsSETargetLowering()
73       setOperationAction(ISD::BITCAST, VecTys[i], Legal);  in MipsSETargetLowering()
76     setTargetDAGCombine(ISD::SHL);  in MipsSETargetLowering()
77     setTargetDAGCombine(ISD::SRA);  in MipsSETargetLowering()
78     setTargetDAGCombine(ISD::SRL);  in MipsSETargetLowering()
79     setTargetDAGCombine(ISD::SETCC);  in MipsSETargetLowering()
80     setTargetDAGCombine(ISD::VSELECT);  in MipsSETargetLowering()
84     setOperationAction(ISD::MUL, MVT::v2i16, Legal);  in MipsSETargetLowering()
95     setTargetDAGCombine(ISD::AND);  in MipsSETargetLowering()
96     setTargetDAGCombine(ISD::OR);  in MipsSETargetLowering()
97     setTargetDAGCombine(ISD::SRA);  in MipsSETargetLowering()
98     setTargetDAGCombine(ISD::VSELECT);  in MipsSETargetLowering()
99     setTargetDAGCombine(ISD::XOR);  in MipsSETargetLowering()
114   setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);  in MipsSETargetLowering()
115   setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);  in MipsSETargetLowering()
116   setOperationAction(ISD::MULHS,              MVT::i32, Custom);  in MipsSETargetLowering()
117   setOperationAction(ISD::MULHU,              MVT::i32, Custom);  in MipsSETargetLowering()
120     setOperationAction(ISD::MUL,              MVT::i64, Legal);  in MipsSETargetLowering()
122     setOperationAction(ISD::MUL,              MVT::i64, Custom);  in MipsSETargetLowering()
125     setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Custom);  in MipsSETargetLowering()
126     setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Custom);  in MipsSETargetLowering()
127     setOperationAction(ISD::MULHS,            MVT::i64, Custom);  in MipsSETargetLowering()
128     setOperationAction(ISD::MULHU,            MVT::i64, Custom);  in MipsSETargetLowering()
129     setOperationAction(ISD::SDIVREM,          MVT::i64, Custom);  in MipsSETargetLowering()
130     setOperationAction(ISD::UDIVREM,          MVT::i64, Custom);  in MipsSETargetLowering()
133   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);  in MipsSETargetLowering()
134   setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);  in MipsSETargetLowering()
136   setOperationAction(ISD::SDIVREM, MVT::i32, Custom);  in MipsSETargetLowering()
137   setOperationAction(ISD::UDIVREM, MVT::i32, Custom);  in MipsSETargetLowering()
138   setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);  in MipsSETargetLowering()
139   setOperationAction(ISD::LOAD,               MVT::i32, Custom);  in MipsSETargetLowering()
140   setOperationAction(ISD::STORE,              MVT::i32, Custom);  in MipsSETargetLowering()
142   setTargetDAGCombine(ISD::ADDE);  in MipsSETargetLowering()
143   setTargetDAGCombine(ISD::SUBE);  in MipsSETargetLowering()
144   setTargetDAGCombine(ISD::MUL);  in MipsSETargetLowering()
146   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);  in MipsSETargetLowering()
147   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);  in MipsSETargetLowering()
148   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);  in MipsSETargetLowering()
151     setOperationAction(ISD::LOAD, MVT::f64, Custom);  in MipsSETargetLowering()
152     setOperationAction(ISD::STORE, MVT::f64, Custom);  in MipsSETargetLowering()
158     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);  in MipsSETargetLowering()
159     setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);  in MipsSETargetLowering()
160     setOperationAction(ISD::MUL, MVT::i32, Legal);  in MipsSETargetLowering()
161     setOperationAction(ISD::MULHS, MVT::i32, Legal);  in MipsSETargetLowering()
162     setOperationAction(ISD::MULHU, MVT::i32, Legal);  in MipsSETargetLowering()
166     setOperationAction(ISD::SDIVREM, MVT::i32, Expand);  in MipsSETargetLowering()
167     setOperationAction(ISD::UDIVREM, MVT::i32, Expand);  in MipsSETargetLowering()
168     setOperationAction(ISD::SDIV, MVT::i32, Legal);  in MipsSETargetLowering()
169     setOperationAction(ISD::UDIV, MVT::i32, Legal);  in MipsSETargetLowering()
170     setOperationAction(ISD::SREM, MVT::i32, Legal);  in MipsSETargetLowering()
171     setOperationAction(ISD::UREM, MVT::i32, Legal);  in MipsSETargetLowering()
175     setOperationAction(ISD::SETCC, MVT::i32, Legal);  in MipsSETargetLowering()
176     setOperationAction(ISD::SELECT, MVT::i32, Legal);  in MipsSETargetLowering()
177     setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);  in MipsSETargetLowering()
179     setOperationAction(ISD::SETCC, MVT::f32, Legal);  in MipsSETargetLowering()
180     setOperationAction(ISD::SELECT, MVT::f32, Legal);  in MipsSETargetLowering()
181     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);  in MipsSETargetLowering()
184     setOperationAction(ISD::SETCC, MVT::f64, Legal);  in MipsSETargetLowering()
185     setOperationAction(ISD::SELECT, MVT::f64, Legal);  in MipsSETargetLowering()
186     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);  in MipsSETargetLowering()
188     setOperationAction(ISD::BRCOND, MVT::Other, Legal);  in MipsSETargetLowering()
191     setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);  in MipsSETargetLowering()
192     setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);  in MipsSETargetLowering()
193     setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);  in MipsSETargetLowering()
194     setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);  in MipsSETargetLowering()
196     setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);  in MipsSETargetLowering()
197     setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);  in MipsSETargetLowering()
198     setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);  in MipsSETargetLowering()
199     setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);  in MipsSETargetLowering()
205     setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);  in MipsSETargetLowering()
206     setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);  in MipsSETargetLowering()
207     setOperationAction(ISD::MUL, MVT::i64, Legal);  in MipsSETargetLowering()
208     setOperationAction(ISD::MULHS, MVT::i64, Legal);  in MipsSETargetLowering()
209     setOperationAction(ISD::MULHU, MVT::i64, Legal);  in MipsSETargetLowering()
213     setOperationAction(ISD::SDIVREM, MVT::i64, Expand);  in MipsSETargetLowering()
214     setOperationAction(ISD::UDIVREM, MVT::i64, Expand);  in MipsSETargetLowering()
215     setOperationAction(ISD::SDIV, MVT::i64, Legal);  in MipsSETargetLowering()
216     setOperationAction(ISD::UDIV, MVT::i64, Legal);  in MipsSETargetLowering()
217     setOperationAction(ISD::SREM, MVT::i64, Legal);  in MipsSETargetLowering()
218     setOperationAction(ISD::UREM, MVT::i64, Legal);  in MipsSETargetLowering()
222     setOperationAction(ISD::SETCC, MVT::i64, Legal);  in MipsSETargetLowering()
223     setOperationAction(ISD::SELECT, MVT::i64, Legal);  in MipsSETargetLowering()
224     setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);  in MipsSETargetLowering()
250   for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)  in addMSAIntType()
253   setOperationAction(ISD::BITCAST, Ty, Legal);  in addMSAIntType()
254   setOperationAction(ISD::LOAD, Ty, Legal);  in addMSAIntType()
255   setOperationAction(ISD::STORE, Ty, Legal);  in addMSAIntType()
256   setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);  in addMSAIntType()
257   setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);  in addMSAIntType()
258   setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);  in addMSAIntType()
260   setOperationAction(ISD::ADD, Ty, Legal);  in addMSAIntType()
261   setOperationAction(ISD::AND, Ty, Legal);  in addMSAIntType()
262   setOperationAction(ISD::CTLZ, Ty, Legal);  in addMSAIntType()
263   setOperationAction(ISD::CTPOP, Ty, Legal);  in addMSAIntType()
264   setOperationAction(ISD::MUL, Ty, Legal);  in addMSAIntType()
265   setOperationAction(ISD::OR, Ty, Legal);  in addMSAIntType()
266   setOperationAction(ISD::SDIV, Ty, Legal);  in addMSAIntType()
267   setOperationAction(ISD::SREM, Ty, Legal);  in addMSAIntType()
268   setOperationAction(ISD::SHL, Ty, Legal);  in addMSAIntType()
269   setOperationAction(ISD::SRA, Ty, Legal);  in addMSAIntType()
270   setOperationAction(ISD::SRL, Ty, Legal);  in addMSAIntType()
271   setOperationAction(ISD::SUB, Ty, Legal);  in addMSAIntType()
272   setOperationAction(ISD::UDIV, Ty, Legal);  in addMSAIntType()
273   setOperationAction(ISD::UREM, Ty, Legal);  in addMSAIntType()
274   setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);  in addMSAIntType()
275   setOperationAction(ISD::VSELECT, Ty, Legal);  in addMSAIntType()
276   setOperationAction(ISD::XOR, Ty, Legal);  in addMSAIntType()
279     setOperationAction(ISD::FP_TO_SINT, Ty, Legal);  in addMSAIntType()
280     setOperationAction(ISD::FP_TO_UINT, Ty, Legal);  in addMSAIntType()
281     setOperationAction(ISD::SINT_TO_FP, Ty, Legal);  in addMSAIntType()
282     setOperationAction(ISD::UINT_TO_FP, Ty, Legal);  in addMSAIntType()
285   setOperationAction(ISD::SETCC, Ty, Legal);  in addMSAIntType()
286   setCondCodeAction(ISD::SETNE, Ty, Expand);  in addMSAIntType()
287   setCondCodeAction(ISD::SETGE, Ty, Expand);  in addMSAIntType()
288   setCondCodeAction(ISD::SETGT, Ty, Expand);  in addMSAIntType()
289   setCondCodeAction(ISD::SETUGE, Ty, Expand);  in addMSAIntType()
290   setCondCodeAction(ISD::SETUGT, Ty, Expand);  in addMSAIntType()
299   for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)  in addMSAFloatType()
302   setOperationAction(ISD::LOAD, Ty, Legal);  in addMSAFloatType()
303   setOperationAction(ISD::STORE, Ty, Legal);  in addMSAFloatType()
304   setOperationAction(ISD::BITCAST, Ty, Legal);  in addMSAFloatType()
305   setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);  in addMSAFloatType()
306   setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);  in addMSAFloatType()
307   setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);  in addMSAFloatType()
310     setOperationAction(ISD::FABS,  Ty, Legal);  in addMSAFloatType()
311     setOperationAction(ISD::FADD,  Ty, Legal);  in addMSAFloatType()
312     setOperationAction(ISD::FDIV,  Ty, Legal);  in addMSAFloatType()
313     setOperationAction(ISD::FEXP2, Ty, Legal);  in addMSAFloatType()
314     setOperationAction(ISD::FLOG2, Ty, Legal);  in addMSAFloatType()
315     setOperationAction(ISD::FMA,   Ty, Legal);  in addMSAFloatType()
316     setOperationAction(ISD::FMUL,  Ty, Legal);  in addMSAFloatType()
317     setOperationAction(ISD::FRINT, Ty, Legal);  in addMSAFloatType()
318     setOperationAction(ISD::FSQRT, Ty, Legal);  in addMSAFloatType()
319     setOperationAction(ISD::FSUB,  Ty, Legal);  in addMSAFloatType()
320     setOperationAction(ISD::VSELECT, Ty, Legal);  in addMSAFloatType()
322     setOperationAction(ISD::SETCC, Ty, Legal);  in addMSAFloatType()
323     setCondCodeAction(ISD::SETOGE, Ty, Expand);  in addMSAFloatType()
324     setCondCodeAction(ISD::SETOGT, Ty, Expand);  in addMSAFloatType()
325     setCondCodeAction(ISD::SETUGE, Ty, Expand);  in addMSAFloatType()
326     setCondCodeAction(ISD::SETUGT, Ty, Expand);  in addMSAFloatType()
327     setCondCodeAction(ISD::SETGE,  Ty, Expand);  in addMSAFloatType()
328     setCondCodeAction(ISD::SETGT,  Ty, Expand);  in addMSAFloatType()
363   case ISD::LOAD:  return lowerLOAD(Op, DAG);  in LowerOperation()
364   case ISD::STORE: return lowerSTORE(Op, DAG);  in LowerOperation()
365   case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);  in LowerOperation()
366   case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);  in LowerOperation()
367   case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);  in LowerOperation()
368   case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);  in LowerOperation()
369   case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);  in LowerOperation()
370   case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);  in LowerOperation()
371   case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,  in LowerOperation()
373   case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);  in LowerOperation()
374   case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);  in LowerOperation()
375   case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);  in LowerOperation()
376   case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);  in LowerOperation()
377   case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);  in LowerOperation()
378   case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);  in LowerOperation()
397   if (ADDCNode->getOpcode() != ISD::ADDC)  in selectMADD()
410   if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)  in selectMADD()
436   MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;  in selectMADD()
469   if (SUBCNode->getOpcode() != ISD::SUBC)  in selectMSUB()
482   if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)  in selectMSUB()
508   MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;  in selectMSUB()
623   if (N->getOpcode() == ISD::BITCAST)  in isVectorAllOnes()
645   if (N->getOpcode() != ISD::XOR)  in isBitwiseInverse()
677   if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {  in performORCombine()
777     return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);  in performORCombine()
811     return DAG.getNode(ISD::SHL, DL, VT, X,  in genConstMult()
824     return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);  in genConstMult()
831   return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);  in genConstMult()
907     if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {  in performSRACombine()
951 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {  in isLegalDSPCondCode()
955   case ISD::SETEQ:  in isLegalDSPCondCode()
956   case ISD::SETNE:  return true;  in isLegalDSPCondCode()
957   case ISD::SETLT:  in isLegalDSPCondCode()
958   case ISD::SETLE:  in isLegalDSPCondCode()
959   case ISD::SETGT:  in isLegalDSPCondCode()
960   case ISD::SETGE:  return IsV216;  in isLegalDSPCondCode()
961   case ISD::SETULT:  in isLegalDSPCondCode()
962   case ISD::SETULE:  in isLegalDSPCondCode()
963   case ISD::SETUGT:  in isLegalDSPCondCode()
964   case ISD::SETUGE: return !IsV216;  in isLegalDSPCondCode()
1000     if (Op0->getOpcode() != ISD::SETCC)  in performVSELECTCombine()
1003     ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();  in performVSELECTCombine()
1006     if (CondCode == ISD::SETLT  || CondCode == ISD::SETLE)  in performVSELECTCombine()
1008     else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)  in performVSELECTCombine()
1050     if (ISD::isBuildVectorAllOnes(Op0.getNode()))  in performXORCombine()
1052     else if (ISD::isBuildVectorAllOnes(Op1.getNode()))  in performXORCombine()
1057     if (NotOp->getOpcode() == ISD::OR)  in performXORCombine()
1071   case ISD::ADDE:  in PerformDAGCombine()
1073   case ISD::AND:  in PerformDAGCombine()
1076   case ISD::OR:  in PerformDAGCombine()
1079   case ISD::SUBE:  in PerformDAGCombine()
1081   case ISD::MUL:  in PerformDAGCombine()
1083   case ISD::SHL:  in PerformDAGCombine()
1085   case ISD::SRA:  in PerformDAGCombine()
1087   case ISD::SRL:  in PerformDAGCombine()
1089   case ISD::VSELECT:  in PerformDAGCombine()
1091   case ISD::XOR:  in PerformDAGCombine()
1094   case ISD::SETCC:  in PerformDAGCombine()
1215   Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));  in lowerLOAD()
1253   Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));  in lowerSTORE()
1285   SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,  in initAccumulator()
1287   SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,  in initAccumulator()
1295   return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);  in extractLOHI()
1321   assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);  in lowerDSPIntr()
1392   SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,  in lowerMSASplatZExt()
1396     Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);  in lowerMSASplatZExt()
1416     SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);  in getBuildVectorSplat()
1417     SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,  in getBuildVectorSplat()
1419     SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);  in getBuildVectorSplat()
1432   SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,  in getBuildVectorSplat()
1436     Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);  in getBuildVectorSplat()
1461           DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,  in lowerMSABinaryBitImmIntr()
1462                       DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,  in lowerMSABinaryBitImmIntr()
1473       Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);  in lowerMSABinaryBitImmIntr()
1478         DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);  in lowerMSABinaryBitImmIntr()
1488   SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));  in lowerMSABitClear()
1490   return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),  in lowerMSABitClear()
1501   return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);  in lowerMSABitClearImm()
1547     return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1553     return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1556     return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1559     return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1580     return DAG.getNode(ISD::VSELECT, DL, VecTy,  in lowerINTRINSIC_WO_CHAIN()
1593     return DAG.getNode(ISD::VSELECT, DL, VecTy,  in lowerINTRINSIC_WO_CHAIN()
1598     return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),  in lowerINTRINSIC_WO_CHAIN()
1601     return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1605     return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),  in lowerINTRINSIC_WO_CHAIN()
1608     return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1618     return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1619                        DAG.getNode(ISD::SHL, DL, VecTy, One,  in lowerINTRINSIC_WO_CHAIN()
1626     return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),  in lowerINTRINSIC_WO_CHAIN()
1639     return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1644     return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1654     return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1655                        DAG.getNode(ISD::SHL, DL, VecTy, One,  in lowerINTRINSIC_WO_CHAIN()
1662     return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),  in lowerINTRINSIC_WO_CHAIN()
1678                         Op->getOperand(2), ISD::SETEQ);  in lowerINTRINSIC_WO_CHAIN()
1684                         lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);  in lowerINTRINSIC_WO_CHAIN()
1690                         Op->getOperand(2), ISD::SETLE);  in lowerINTRINSIC_WO_CHAIN()
1696                         lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);  in lowerINTRINSIC_WO_CHAIN()
1702                         Op->getOperand(2), ISD::SETULE);  in lowerINTRINSIC_WO_CHAIN()
1708                         lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);  in lowerINTRINSIC_WO_CHAIN()
1714                         Op->getOperand(2), ISD::SETLT);  in lowerINTRINSIC_WO_CHAIN()
1720                         lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);  in lowerINTRINSIC_WO_CHAIN()
1726                         Op->getOperand(2), ISD::SETULT);  in lowerINTRINSIC_WO_CHAIN()
1732                         lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);  in lowerINTRINSIC_WO_CHAIN()
1744       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),  in lowerINTRINSIC_WO_CHAIN()
1762       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),  in lowerINTRINSIC_WO_CHAIN()
1770     return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1776     return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1780     return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1786                         Op->getOperand(2), ISD::SETOEQ);  in lowerINTRINSIC_WO_CHAIN()
1790                         Op->getOperand(2), ISD::SETOLE);  in lowerINTRINSIC_WO_CHAIN()
1794                         Op->getOperand(2), ISD::SETOLT);  in lowerINTRINSIC_WO_CHAIN()
1798                         Op->getOperand(2), ISD::SETONE);  in lowerINTRINSIC_WO_CHAIN()
1802                         Op->getOperand(2), ISD::SETO);  in lowerINTRINSIC_WO_CHAIN()
1806                         Op->getOperand(2), ISD::SETUEQ);  in lowerINTRINSIC_WO_CHAIN()
1810                         Op->getOperand(2), ISD::SETULE);  in lowerINTRINSIC_WO_CHAIN()
1814                         Op->getOperand(2), ISD::SETULT);  in lowerINTRINSIC_WO_CHAIN()
1818                         Op->getOperand(2), ISD::SETUO);  in lowerINTRINSIC_WO_CHAIN()
1822                         Op->getOperand(2), ISD::SETUNE);  in lowerINTRINSIC_WO_CHAIN()
1825     return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1829     return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1833     return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1845     return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);  in lowerINTRINSIC_WO_CHAIN()
1851         ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1852         DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));  in lowerINTRINSIC_WO_CHAIN()
1856     return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));  in lowerINTRINSIC_WO_CHAIN()
1859     return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1863     return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1868     return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1869                        DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,  in lowerINTRINSIC_WO_CHAIN()
1874     return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));  in lowerINTRINSIC_WO_CHAIN()
1877     return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));  in lowerINTRINSIC_WO_CHAIN()
1880     return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1884     return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1888     return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1918     return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
1935     return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1936                        DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,  in lowerINTRINSIC_WO_CHAIN()
1944     return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
1945                        DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,  in lowerINTRINSIC_WO_CHAIN()
2000     return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2006     return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2012     return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2019     return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2020                        DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,  in lowerINTRINSIC_WO_CHAIN()
2027     return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));  in lowerINTRINSIC_WO_CHAIN()
2029     SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2034     SDValue Res =  DAG.getNode(ISD::OR, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2040     return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2043     return DAG.getNode(ISD::OR, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2061     return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));  in lowerINTRINSIC_WO_CHAIN()
2071     return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2077     return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2101     return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2107     return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2113     return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2119     return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2125     return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2131     return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2140     return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2143     return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()
2156   Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);  in lowerMSALoadIntr()
2224   Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);  in lowerMSAStoreIntr()
2290   if (Op->getOpcode() == ISD::UNDEF)  in isConstantOrUndef()
2370       Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);  in lowerBUILD_VECTOR()
2386       Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,  in lowerBUILD_VECTOR()
2670   SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);  in lowerVECTOR_SHUFFLE_VSHF()