678     SDValue Op0Op0 = Op0->getOperand(0);  in performORCombine()  local
692     if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {  in performORCombine()
693       Cond = Op0Op0;  in performORCombine()
711       IfSet = Op0Op0;  in performORCombine()
727       if (isBitwiseInverse(Op0Op0, Op1Op0)) {  in performORCombine()
734         IfClr = Op0Op0;  in performORCombine()
735       } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {  in performORCombine()
742         IfClr = Op0Op0;  in performORCombine()
743       } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {  in performORCombine()
744         Cond = Op0Op0;  in performORCombine()
747       } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {  in performORCombine()
748         Cond = Op0Op0;  in performORCombine()
753         IfSet = Op0Op0;  in performORCombine()
757         IfSet = Op0Op0;  in performORCombine()
908       SDValue Op0Op0 = Op0->getOperand(0);  in performSRACombine()  local
914       if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&  in performSRACombine()
915           Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)  in performSRACombine()
918       EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();  in performSRACombine()
922           (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&  in performSRACombine()
924         SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),  in performSRACombine()
925                           Op0Op0->getOperand(2) };  in performSRACombine()
926         return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),  in performSRACombine()
927                            Op0Op0->getVTList(),  in performSRACombine()
928                            makeArrayRef(Ops, Op0Op0->getNumOperands()));  in performSRACombine()
1015     SDValue Op0Op0 = Op0->getOperand(0);  in performVSELECTCombine()  local
1018     if (Op1 == Op0Op0 && Op2 == Op0Op1)  in performVSELECTCombine()
1021     else if (Op1 == Op0Op1 && Op2 == Op0Op0)  in performVSELECTCombine()