Lines Matching refs:InsIdx

2066   unsigned InsIdx = 0;  in LowerFormalArguments()  local
2069 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) { in LowerFormalArguments()
2093 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT)); in LowerFormalArguments()
2094 ++InsIdx; in LowerFormalArguments()
2097 --InsIdx; in LowerFormalArguments()
2104 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT)); in LowerFormalArguments()
2105 ++InsIdx; in LowerFormalArguments()
2108 --InsIdx; in LowerFormalArguments()
2111 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT)); in LowerFormalArguments()
2148 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) { in LowerFormalArguments()
2149 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2151 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr, in LowerFormalArguments()
2162 ++InsIdx; in LowerFormalArguments()
2165 --InsIdx; in LowerFormalArguments()
2189 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) in LowerFormalArguments()
2190 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P); in LowerFormalArguments()
2192 ++InsIdx; in LowerFormalArguments()
2211 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) { in LowerFormalArguments()
2212 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); in LowerFormalArguments()
2213 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1); in LowerFormalArguments()
2218 InsIdx += 2; in LowerFormalArguments()
2255 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) in LowerFormalArguments()
2256 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt); in LowerFormalArguments()
2261 InsIdx += NumElts; in LowerFormalArguments()
2265 --InsIdx; in LowerFormalArguments()
2275 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) { in LowerFormalArguments()
2276 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2278 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg, in LowerFormalArguments()
2283 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg, in LowerFormalArguments()
2301 assert(ObjectVT == Ins[InsIdx].VT && in LowerFormalArguments()