Lines Matching refs:dst2

1778       NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1780 "\t{{$dst, $dst2}}, [retval0+$b];"), []>;
1783 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1787 "\t{{$dst, $dst2, $dst3, $dst4}}, [retval0+$b];"), []>;
2155 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2159 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2160 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2164 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2165 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2169 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2170 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2174 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2175 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2179 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2180 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2184 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2185 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2190 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2191 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2196 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2197 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2202 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2203 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2208 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2210 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2215 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2217 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2222 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),