524   const DataLayout *DL = getDataLayout();  in isZExtFree()  local
525   unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());  in isZExtFree()
526   unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());  in isZExtFree()
569                                      SDLoc DL, SelectionDAG &DAG) const {  in LowerReturn()  argument
570   return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);  in LowerReturn()
677   SDLoc DL(InitPtr);  in LowerConstantInitializer()  local
683     return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,  in LowerConstantInitializer()
691     return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,  in LowerConstantInitializer()
704       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);  in LowerConstantInitializer()
710     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);  in LowerConstantInitializer()
728       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);  in LowerConstantInitializer()
734     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);  in LowerConstantInitializer()
740     return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,  in LowerConstantInitializer()
880   SDLoc DL(Op);  in LowerINTRINSIC_WO_CHAIN()  local
893       return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
914       return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,  in LowerINTRINSIC_WO_CHAIN()
919       return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
924       return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
928       return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
932       return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
935       return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
938       return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
946         SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
947         SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,  in LowerINTRINSIC_WO_CHAIN()
949         return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,  in LowerINTRINSIC_WO_CHAIN()
952         return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
956       return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),  in LowerINTRINSIC_WO_CHAIN()
960       return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),  in LowerINTRINSIC_WO_CHAIN()
963       return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),  in LowerINTRINSIC_WO_CHAIN()
966       return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),  in LowerINTRINSIC_WO_CHAIN()
969       return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),  in LowerINTRINSIC_WO_CHAIN()
973       return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
977       return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
981       return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
985       return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
989       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
992       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
995       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
998       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
1001       return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
1007       return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
1013       return DAG.getNode(AMDGPUISD::BFI, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
1019       return DAG.getNode(AMDGPUISD::BFM, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
1024       return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
1027     return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
1031       return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
1034       return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
1036       return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
1043   SDLoc DL(Op);  in LowerIntrinsicIABS()  local
1045   SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),  in LowerIntrinsicIABS()
1048   return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));  in LowerIntrinsicIABS()
1055   SDLoc DL(Op);  in LowerIntrinsicLRP()  local
1057   SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,  in LowerIntrinsicLRP()
1060   SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,  in LowerIntrinsicLRP()
1062   return DAG.getNode(ISD::FADD, DL, VT,  in LowerIntrinsicLRP()
1063       DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),  in LowerIntrinsicLRP()
1068 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,  in CombineFMinMaxLegacy()  argument
1101       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1102     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1120       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1121     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1126       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1127     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1138       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1139     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1148 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,  in CombineIMinMax()  argument
1164     return DAG.getNode(Opc, DL, VT, LHS, RHS);  in CombineIMinMax()
1169     return DAG.getNode(Opc, DL, VT, LHS, RHS);  in CombineIMinMax()
1174     return DAG.getNode(Opc, DL, VT, LHS, RHS);  in CombineIMinMax()
1179     return DAG.getNode(Opc, DL, VT, LHS, RHS);  in CombineIMinMax()
1288   SDLoc DL(Op);  in MergeVectorStore()  local
1303     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,  in MergeVectorStore()
1305     Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);  in MergeVectorStore()
1306     Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg  in MergeVectorStore()
1309     Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);  in MergeVectorStore()
1314       PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);  in MergeVectorStore()
1320     return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,  in MergeVectorStore()
1327   return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,  in MergeVectorStore()
1416   SDLoc DL(Op);  in LowerLOAD()  local
1431     SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,  in LowerLOAD()
1435       DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),  in LowerLOAD()
1439     return DAG.getMergeValues(Ops, DL);  in LowerLOAD()
1448   SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),  in LowerLOAD()
1450   SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),  in LowerLOAD()
1454   SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,  in LowerLOAD()
1457   SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,  in LowerLOAD()
1460   Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);  in LowerLOAD()
1467       DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),  in LowerLOAD()
1471     return DAG.getMergeValues(Ops, DL);  in LowerLOAD()
1475     DAG.getZeroExtendInReg(Ret, DL, MemEltVT),  in LowerLOAD()
1479   return DAG.getMergeValues(Ops, DL);  in LowerLOAD()
1483   SDLoc DL(Op);  in LowerSTORE()  local
1507     SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,  in LowerSTORE()
1509     SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,  in LowerSTORE()
1512     SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,  in LowerSTORE()
1515     SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,  in LowerSTORE()
1518     SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,  in LowerSTORE()
1521     SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);  in LowerSTORE()
1523     SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,  in LowerSTORE()
1526     SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),  in LowerSTORE()
1528     DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,  in LowerSTORE()
1530     Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);  in LowerSTORE()
1532     SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);  in LowerSTORE()
1533     return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,  in LowerSTORE()
1543   SDLoc DL(Op);  in LowerDIVREM24()  local
1565     jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);  in LowerDIVREM24()
1568     jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));  in LowerDIVREM24()
1571     jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));  in LowerDIVREM24()
1574     jq = DAG.getSExtOrTrunc(jq, DL, IntVT);  in LowerDIVREM24()
1579     DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);  in LowerDIVREM24()
1583     DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);  in LowerDIVREM24()
1586   SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);  in LowerDIVREM24()
1589   SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);  in LowerDIVREM24()
1592   SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,  in LowerDIVREM24()
1593                            fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));  in LowerDIVREM24()
1596   fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);  in LowerDIVREM24()
1599   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);  in LowerDIVREM24()
1602   SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,  in LowerDIVREM24()
1603                            DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);  in LowerDIVREM24()
1606   SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);  in LowerDIVREM24()
1609   fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);  in LowerDIVREM24()
1612   fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);  in LowerDIVREM24()
1617   SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);  in LowerDIVREM24()
1620   jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));  in LowerDIVREM24()
1623   iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);  in LowerDIVREM24()
1626   SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);  in LowerDIVREM24()
1629   SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);  in LowerDIVREM24()
1630   Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);  in LowerDIVREM24()
1636   return DAG.getMergeValues(Res, DL);  in LowerDIVREM24()
1644   SDLoc DL(Op);  in LowerUDIVREM64()  local
1653   SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);  in LowerUDIVREM64()
1654   SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);  in LowerUDIVREM64()
1657   SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);  in LowerUDIVREM64()
1658   SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);  in LowerUDIVREM64()
1664     SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),  in LowerUDIVREM64()
1667     SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);  in LowerUDIVREM64()
1668     SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);  in LowerUDIVREM64()
1675   SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);  in LowerUDIVREM64()
1676   SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);  in LowerUDIVREM64()
1678   SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);  in LowerUDIVREM64()
1679   SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);  in LowerUDIVREM64()
1681   SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);  in LowerUDIVREM64()
1690     SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);  in LowerUDIVREM64()
1691     HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);  in LowerUDIVREM64()
1692     HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);  in LowerUDIVREM64()
1695     REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, VT));  in LowerUDIVREM64()
1697     REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);  in LowerUDIVREM64()
1700     SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);  in LowerUDIVREM64()
1702     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);  in LowerUDIVREM64()
1705     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);  in LowerUDIVREM64()
1706     REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);  in LowerUDIVREM64()
1709   SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);  in LowerUDIVREM64()
1716   SDLoc DL(Op);  in LowerUDIVREM()  local
1722     return DAG.getMergeValues(Results, DL);  in LowerUDIVREM()
1740   SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);  in LowerUDIVREM()
1743   SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);  in LowerUDIVREM()
1746   SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);  in LowerUDIVREM()
1749   SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),  in LowerUDIVREM()
1753   SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),  in LowerUDIVREM()
1758   SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);  in LowerUDIVREM()
1761   SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);  in LowerUDIVREM()
1764   SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);  in LowerUDIVREM()
1767   SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),  in LowerUDIVREM()
1771   SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);  in LowerUDIVREM()
1774   SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);  in LowerUDIVREM()
1777   SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);  in LowerUDIVREM()
1780   SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,  in LowerUDIVREM()
1785   SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,  in LowerUDIVREM()
1791   SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,  in LowerUDIVREM()
1797   SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,  in LowerUDIVREM()
1801   SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,  in LowerUDIVREM()
1805   SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),  in LowerUDIVREM()
1809   Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),  in LowerUDIVREM()
1815   SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);  in LowerUDIVREM()
1818   SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);  in LowerUDIVREM()
1821   SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),  in LowerUDIVREM()
1825   Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),  in LowerUDIVREM()
1831   return DAG.getMergeValues(Ops, DL);  in LowerUDIVREM()
1836   SDLoc DL(Op);  in LowerSDIVREM()  local
1856     SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);  in LowerSDIVREM()
1857     SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);  in LowerSDIVREM()
1858     SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),  in LowerSDIVREM()
1861       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),  in LowerSDIVREM()
1862       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))  in LowerSDIVREM()
1864     return DAG.getMergeValues(Res, DL);  in LowerSDIVREM()
1867   SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);  in LowerSDIVREM()
1868   SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);  in LowerSDIVREM()
1869   SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);  in LowerSDIVREM()
1872   LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);  in LowerSDIVREM()
1873   RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);  in LowerSDIVREM()
1875   LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);  in LowerSDIVREM()
1876   RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);  in LowerSDIVREM()
1878   SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);  in LowerSDIVREM()
1881   Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);  in LowerSDIVREM()
1882   Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);  in LowerSDIVREM()
1884   Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);  in LowerSDIVREM()
1885   Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);  in LowerSDIVREM()
1891   return DAG.getMergeValues(Res, DL);  in LowerSDIVREM()
2176   SDLoc DL(Op);  in LowerUINT_TO_FP()  local
2179   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,  in LowerUINT_TO_FP()
2181   SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);  in LowerUINT_TO_FP()
2182   SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,  in LowerUINT_TO_FP()
2184   SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);  in LowerUINT_TO_FP()
2185   FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,  in LowerUINT_TO_FP()
2187   return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);  in LowerUINT_TO_FP()
2258   SDLoc DL(Op);  in LowerSIGN_EXTEND_INREG()  local
2267     Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);  in LowerSIGN_EXTEND_INREG()
2269   return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);  in LowerSIGN_EXTEND_INREG()
2378   SDLoc DL(N);  in performMulCombine()  local
2385     N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);  in performMulCombine()
2386     N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);  in performMulCombine()
2387     Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);  in performMulCombine()
2389     N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);  in performMulCombine()
2390     N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);  in performMulCombine()
2391     Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);  in performMulCombine()
2398   return DAG.getSExtOrTrunc(Mul, DL, VT);  in performMulCombine()
2404   SDLoc DL(N);  in PerformDAGCombine()  local
2421       SDLoc DL(N);  in PerformDAGCombine()  local
2431         return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);  in PerformDAGCombine()
2436         return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);  in PerformDAGCombine()
2479         return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,  in PerformDAGCombine()
2483       return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);  in PerformDAGCombine()
2502       return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,  in PerformDAGCombine()