Lines Matching refs:SDValue
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
34 SDValue Chain,
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
62 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
63 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
65 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
67 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
78 SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
81 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
84 SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
87 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
94 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
95 SmallVectorImpl<SDValue> &Results) const;
96 bool isHWTrueValue(SDValue Op) const;
97 bool isHWFalseValue(SDValue Op) const;
122 bool isZExtFree(SDValue Val, EVT VT2) const override;
139 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
142 const SmallVectorImpl<SDValue> &OutVals,
144 SDValue LowerCall(CallLoweringInfo &CLI,
145 SmallVectorImpl<SDValue> &InVals) const override;
147 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
148 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
150 SmallVectorImpl<SDValue> &Results,
153 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
155 SDValue CombineFMinMaxLegacy(SDLoc DL,
157 SDValue LHS,
158 SDValue RHS,
159 SDValue True,
160 SDValue False,
161 SDValue CC,
163 SDValue CombineIMinMax(SDLoc DL,
165 SDValue LHS,
166 SDValue RHS,
167 SDValue True,
168 SDValue False,
169 SDValue CC,
174 SDValue getRsqrtEstimate(SDValue Operand,
178 SDValue getRecipEstimate(SDValue Operand,
190 void computeKnownBitsForTargetNode(const SDValue Op,
196 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
203 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,