Lines Matching refs:AMDGPUOperand
40 class AMDGPUOperand : public MCParsedAsmOperand { class
51 AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {} in AMDGPUOperand() function in __anondcc3d2080111::AMDGPUOperand
242 static std::unique_ptr<AMDGPUOperand> CreateImm(int64_t Val, SMLoc Loc, in CreateImm()
245 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate); in CreateImm()
254 static std::unique_ptr<AMDGPUOperand> CreateToken(StringRef Str, SMLoc Loc, in CreateToken()
256 auto Res = llvm::make_unique<AMDGPUOperand>(Token); in CreateToken()
264 static std::unique_ptr<AMDGPUOperand> CreateReg(unsigned RegNo, SMLoc S, in CreateReg()
267 auto Op = llvm::make_unique<AMDGPUOperand>(Register); in CreateReg()
276 static std::unique_ptr<AMDGPUOperand> CreateExpr(const class MCExpr *Expr, SMLoc S) { in CreateExpr()
277 auto Op = llvm::make_unique<AMDGPUOperand>(Expression); in CreateExpr()
342 enum AMDGPUOperand::ImmTy ImmTy =
343 AMDGPUOperand::ImmTyNone);
345 enum AMDGPUOperand::ImmTy ImmTy =
346 AMDGPUOperand::ImmTyNone);
379 AMDGPUOperand::ImmTy Type;
531 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
548 const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]); in operandsHaveModifiers()
551 if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod || in operandsHaveModifiers()
552 Op.getImmTy() == AMDGPUOperand::ImmTyClamp)) in operandsHaveModifiers()
600 Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S)); in parseOperand()
615 AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S)); in parseOperand()
643 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]); in parseOperand()
649 Operands.push_back(AMDGPUOperand::CreateReg( in parseOperand()
653 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]); in parseOperand()
658 Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(), in parseOperand()
682 Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc)); in ParseInstruction()
750 enum AMDGPUOperand::ImmTy ImmTy) { in parseIntWithPrefix()
759 Operands.push_back(AMDGPUOperand::CreateImm(Offset, S, ImmTy)); in parseIntWithPrefix()
765 enum AMDGPUOperand::ImmTy ImmTy) { in parseNamedBit()
791 Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy)); in parseNamedBit()
798 const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]); in operandsHasOptionalOp()
835 Operands.push_back(AMDGPUOperand::CreateImm(Value, S, Op.Type)); in parseOptionalOps()
846 {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
847 {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
851 {"offset0", AMDGPUOperand::ImmTyDSOffset0, false, 0, nullptr},
852 {"offset1", AMDGPUOperand::ImmTyDSOffset1, false, 0, nullptr},
853 {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
869 parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset); in parseDSOffsetOptional()
871 Operands.push_back(AMDGPUOperand::CreateImm(0, S, in parseDSOffsetOptional()
872 AMDGPUOperand::ImmTyOffset)); in parseDSOffsetOptional()
878 bool AMDGPUOperand::isDSOffset() const { in isDSOffset()
882 bool AMDGPUOperand::isDSOffset01() const { in isDSOffset01()
889 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx; in cvtDSOffset01()
892 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtDSOffset01()
904 unsigned Offset0Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset0]; in cvtDSOffset01()
905 unsigned Offset1Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset1]; in cvtDSOffset01()
906 unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS]; in cvtDSOffset01()
908 ((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0 in cvtDSOffset01()
909 ((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1 in cvtDSOffset01()
910 ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds in cvtDSOffset01()
916 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx; in cvtDS()
920 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtDS()
937 unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset]; in cvtDS()
938 ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1); // offset in cvtDS()
941 unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS]; in cvtDS()
942 ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds in cvtDS()
1019 Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S)); in parseSWaitCntOps()
1023 bool AMDGPUOperand::isSWaitCnt() const { in isSWaitCnt()
1041 Operands.push_back(AMDGPUOperand::CreateImm(Imm, S)); in parseSOppBrTarget()
1046 Operands.push_back(AMDGPUOperand::CreateExpr( in parseSOppBrTarget()
1059 {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
1060 {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
1061 {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
1062 {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
1090 bool AMDGPUOperand::isMubufOffset() const { in isMubufOffset()
1096 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx; in cvtMubuf()
1099 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtMubuf()
1108 if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) { in cvtMubuf()
1126 unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset]; in cvtMubuf()
1127 unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC]; in cvtMubuf()
1128 unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC]; in cvtMubuf()
1129 unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE]; in cvtMubuf()
1131 ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1); in cvtMubuf()
1132 ((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1); in cvtMubuf()
1133 ((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1); in cvtMubuf()
1134 ((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1); in cvtMubuf()
1183 {"clamp", AMDGPUOperand::ImmTyClamp, true, 0, nullptr},
1184 {"mul", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodMul},
1185 {"div", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodDiv},
1192 AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]); in isVOP3()
1201 AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]); in isVOP3()
1228 AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]); in parseVOP3OptionalOps()
1239 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1); in cvtVOP3()
1242 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx; in cvtVOP3()
1246 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtVOP3()
1249 ((AMDGPUOperand &)*Operands[i]).addRegWithInputModsOperands(Inst, 2); in cvtVOP3()
1255 unsigned ClampIdx = OptionalIdx[AMDGPUOperand::ImmTyClamp]; in cvtVOP3()
1256 unsigned OModIdx = OptionalIdx[AMDGPUOperand::ImmTyOMod]; in cvtVOP3()
1258 ((AMDGPUOperand &)*Operands[ClampIdx]).addImmOperands(Inst, 1); in cvtVOP3()
1259 ((AMDGPUOperand &)*Operands[OModIdx]).addImmOperands(Inst, 1); in cvtVOP3()
1262 ((AMDGPUOperand &)*Operands[i]).addRegOrImmOperands(Inst, 1); in cvtVOP3()