330                                OperandVector &Operands, MCStreamer &Out,
334   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
336                         SMLoc NameLoc, OperandVector &Operands) override;
341                                           OperandVector &Operands,
344   OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
349                                    OperandVector &Operands);
352   void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
353   void cvtDS(MCInst &Inst, const OperandVector &Operands);
354   OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
355   OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
356   OperandMatchResultTy parseDSOffsetOptional(OperandVector &Operands);
359   OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
360   OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
362   void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
363   OperandMatchResultTy parseOffset(OperandVector &Operands);
364   OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands);
365   OperandMatchResultTy parseGLC(OperandVector &Operands);
366   OperandMatchResultTy parseSLC(OperandVector &Operands);
367   OperandMatchResultTy parseTFE(OperandVector &Operands);
369   OperandMatchResultTy parseDMask(OperandVector &Operands);
370   OperandMatchResultTy parseUNorm(OperandVector &Operands);
371   OperandMatchResultTy parseR128(OperandVector &Operands);
373   void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
374   OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
506                                               OperandVector &Operands,  in MatchAndEmitInstruction()  argument
512   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {  in MatchAndEmitInstruction()
527         if (ErrorInfo >= Operands.size()) {  in MatchAndEmitInstruction()
531         ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();  in MatchAndEmitInstruction()
545 static bool operandsHaveModifiers(const OperandVector &Operands) {  in operandsHaveModifiers()  argument
547   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {  in operandsHaveModifiers()
548     const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);  in operandsHaveModifiers()
559 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {  in parseOperand()  argument
562   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);  in parseOperand()
600       Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));  in parseOperand()
614       Operands.push_back(  in parseOperand()
623         bool HasModifiers = operandsHaveModifiers(Operands);  in parseOperand()
640           for (unsigned PrevRegIdx = Operands.size() - 1; PrevRegIdx > 1;  in parseOperand()
643             AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]);  in parseOperand()
649         Operands.push_back(AMDGPUOperand::CreateReg(  in parseOperand()
653           AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]);  in parseOperand()
658       Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),  in parseOperand()
671                                        SMLoc NameLoc, OperandVector &Operands) {  in ParseInstruction()  argument
682   Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));  in ParseInstruction()
685     AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);  in ParseInstruction()
703   while ((Res = parseOperand(Operands, Name)) != MatchOperand_NoMatch) {  in ParseInstruction()
749 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,  in parseIntWithPrefix()  argument
759   Operands.push_back(AMDGPUOperand::CreateImm(Offset, S, ImmTy));  in parseIntWithPrefix()
764 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,  in parseNamedBit()  argument
791   Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));  in parseNamedBit()
795 static bool operandsHasOptionalOp(const OperandVector &Operands,  in operandsHasOptionalOp()  argument
797   for (unsigned i = 0; i < Operands.size(); i++) {  in operandsHasOptionalOp()
798     const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]);  in operandsHasOptionalOp()
809                                    OperandVector &Operands) {  in parseOptionalOps()  argument
812     if (operandsHasOptionalOp(Operands, Op))  in parseOptionalOps()
817       Res = parseNamedBit(Op.Name, Operands, Op.Type);  in parseOptionalOps()
835     Operands.push_back(AMDGPUOperand::CreateImm(Value, S, Op.Type));  in parseOptionalOps()
857 AMDGPUAsmParser::parseDSOptionalOps(OperandVector &Operands) {  in parseDSOptionalOps()  argument
858   return parseOptionalOps(DSOptionalOps, Operands);  in parseDSOptionalOps()
861 AMDGPUAsmParser::parseDSOff01OptionalOps(OperandVector &Operands) {  in parseDSOff01OptionalOps()  argument
862   return parseOptionalOps(DSOptionalOpsOff01, Operands);  in parseDSOff01OptionalOps()
866 AMDGPUAsmParser::parseDSOffsetOptional(OperandVector &Operands) {  in parseDSOffsetOptional()  argument
869     parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);  in parseDSOffsetOptional()
871     Operands.push_back(AMDGPUOperand::CreateImm(0, S,  in parseDSOffsetOptional()
887                                     const OperandVector &Operands) {  in cvtDSOffset01()  argument
891   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtDSOffset01()
892     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtDSOffset01()
908   ((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0  in cvtDSOffset01()
909   ((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1  in cvtDSOffset01()
910   ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds  in cvtDSOffset01()
914 void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {  in cvtDS()  argument
919   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtDS()
920     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtDS()
938   ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1); // offset  in cvtDS()
942     ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds  in cvtDS()
996 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {  in parseSWaitCntOps()  argument
1019   Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S));  in parseSWaitCntOps()
1032 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {  in parseSOppBrTarget()  argument
1041       Operands.push_back(AMDGPUOperand::CreateImm(Imm, S));  in parseSOppBrTarget()
1046       Operands.push_back(AMDGPUOperand::CreateExpr(  in parseSOppBrTarget()
1066 AMDGPUAsmParser::parseMubufOptionalOps(OperandVector &Operands) {  in parseMubufOptionalOps()  argument
1067   return parseOptionalOps(MubufOptionalOps, Operands);  in parseMubufOptionalOps()
1071 AMDGPUAsmParser::parseOffset(OperandVector &Operands) {  in parseOffset()  argument
1072   return parseIntWithPrefix("offset", Operands);  in parseOffset()
1076 AMDGPUAsmParser::parseGLC(OperandVector &Operands) {  in parseGLC()  argument
1077   return parseNamedBit("glc", Operands);  in parseGLC()
1081 AMDGPUAsmParser::parseSLC(OperandVector &Operands) {  in parseSLC()  argument
1082   return parseNamedBit("slc", Operands);  in parseSLC()
1086 AMDGPUAsmParser::parseTFE(OperandVector &Operands) {  in parseTFE()  argument
1087   return parseNamedBit("tfe", Operands);  in parseTFE()
1095                                const OperandVector &Operands) {  in cvtMubuf()  argument
1098   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtMubuf()
1099     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtMubuf()
1131   ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1);  in cvtMubuf()
1132   ((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);  in cvtMubuf()
1133   ((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);  in cvtMubuf()
1134   ((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);  in cvtMubuf()
1142 AMDGPUAsmParser::parseDMask(OperandVector &Operands) {  in parseDMask()  argument
1143   return parseIntWithPrefix("dmask", Operands);  in parseDMask()
1147 AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {  in parseUNorm()  argument
1148   return parseNamedBit("unorm", Operands);  in parseUNorm()
1152 AMDGPUAsmParser::parseR128(OperandVector &Operands) {  in parseR128()  argument
1153   return parseNamedBit("r128", Operands);  in parseR128()
1188 static bool isVOP3(OperandVector &Operands) {  in isVOP3()  argument
1189   if (operandsHaveModifiers(Operands))  in isVOP3()
1192   AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);  in isVOP3()
1197   if (Operands.size() >= 5)  in isVOP3()
1200   if (Operands.size() > 3) {  in isVOP3()
1201     AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]);  in isVOP3()
1210 AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) {  in parseVOP3OptionalOps()  argument
1214   bool HasModifiers = operandsHaveModifiers(Operands);  in parseVOP3OptionalOps()
1216   bool IsVOP3 = isVOP3(Operands);  in parseVOP3OptionalOps()
1222         parseOptionalOps(VOP3OptionalOps, Operands);  in parseVOP3OptionalOps()
1227       for (unsigned i = 2, e = Operands.size(); i != e; ++i) {  in parseVOP3OptionalOps()
1228         AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);  in parseVOP3OptionalOps()
1238 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {  in cvtVOP3()  argument
1239   ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1);  in cvtVOP3()
1244   if (operandsHaveModifiers(Operands)) {  in cvtVOP3()
1245     for (unsigned e = Operands.size(); i != e; ++i) {  in cvtVOP3()
1246       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtVOP3()
1249         ((AMDGPUOperand &)*Operands[i]).addRegWithInputModsOperands(Inst, 2);  in cvtVOP3()
1258     ((AMDGPUOperand &)*Operands[ClampIdx]).addImmOperands(Inst, 1);  in cvtVOP3()
1259     ((AMDGPUOperand &)*Operands[OModIdx]).addImmOperands(Inst, 1);  in cvtVOP3()
1261     for (unsigned e = Operands.size(); i != e; ++i)  in cvtVOP3()
1262       ((AMDGPUOperand &)*Operands[i]).addRegOrImmOperands(Inst, 1);  in cvtVOP3()