Lines Matching refs:BUILD_VECTOR

699       return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,  in LowerOperation()
1353       SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);  in LowerSTORE()
1531       Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,  in LowerLOAD()
1613     LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);  in LowerLOAD()
1727   assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);  in CompactSwizzlableVector()
1763   return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),  in CompactSwizzlableVector()
1769   assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);  in ReorganizeVector()
1801   return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),  in ReorganizeVector()
1808   assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);  in OptimizeSwizzle()
1895     if (!isOperationLegal(ISD::BUILD_VECTOR, VT))  in PerformDAGCombine()
1907     if (InVec.getOpcode() == ISD::BUILD_VECTOR) {  in PerformDAGCombine()
1930     return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);  in PerformDAGCombine()
1937     if (Arg.getOpcode() == ISD::BUILD_VECTOR) {  in PerformDAGCombine()
1944         Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {  in PerformDAGCombine()
2003     if (Arg.getOpcode() != ISD::BUILD_VECTOR)  in PerformDAGCombine()
2022     if (Arg.getOpcode() != ISD::BUILD_VECTOR)  in PerformDAGCombine()