Lines Matching refs:ISD
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand); in R600TargetLowering()
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand); in R600TargetLowering()
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); in R600TargetLowering()
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); in R600TargetLowering()
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
64 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
65 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in R600TargetLowering()
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in R600TargetLowering()
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
74 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in R600TargetLowering()
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in R600TargetLowering()
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom); in R600TargetLowering()
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
83 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
84 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); in R600TargetLowering()
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in R600TargetLowering()
89 setOperationAction(ISD::SELECT, MVT::i32, Expand); in R600TargetLowering()
90 setOperationAction(ISD::SELECT, MVT::f32, Expand); in R600TargetLowering()
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); in R600TargetLowering()
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); in R600TargetLowering()
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand); in R600TargetLowering()
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand); in R600TargetLowering()
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
119 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
120 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
121 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
130 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
131 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
134 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
135 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
139 setOperationAction(ISD::STORE, MVT::i8, Custom); in R600TargetLowering()
140 setOperationAction(ISD::STORE, MVT::i32, Custom); in R600TargetLowering()
141 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in R600TargetLowering()
142 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in R600TargetLowering()
146 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
147 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
148 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
152 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
153 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
155 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
157 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
158 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
160 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
161 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
162 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
163 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
164 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
166 setOperationAction(ISD::SUB, MVT::i64, Expand); in R600TargetLowering()
170 setOperationAction(ISD::UDIV, MVT::i64, Custom); in R600TargetLowering()
171 setOperationAction(ISD::UREM, MVT::i64, Custom); in R600TargetLowering()
172 setOperationAction(ISD::SDIV, MVT::i64, Custom); in R600TargetLowering()
173 setOperationAction(ISD::SREM, MVT::i64, Custom); in R600TargetLowering()
177 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in R600TargetLowering()
178 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in R600TargetLowering()
179 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in R600TargetLowering()
181 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
185 setOperationAction(ISD::ADDC, VT, Expand); in R600TargetLowering()
186 setOperationAction(ISD::SUBC, VT, Expand); in R600TargetLowering()
187 setOperationAction(ISD::ADDE, VT, Expand); in R600TargetLowering()
188 setOperationAction(ISD::SUBE, VT, Expand); in R600TargetLowering()
583 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
584 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
585 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG); in LowerOperation()
586 case ISD::SRA_PARTS: in LowerOperation()
587 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG); in LowerOperation()
588 case ISD::FCOS: in LowerOperation()
589 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
590 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
591 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
592 case ISD::LOAD: { in LowerOperation()
600 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
601 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG); in LowerOperation()
602 case ISD::INTRINSIC_VOID: { in LowerOperation()
633 case ISD::INTRINSIC_WO_CHAIN: { in LowerOperation()
699 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
777 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
787 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
859 case ISD::FP_TO_UINT: in ReplaceNodeResults()
867 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
873 case ISD::UDIV: { in ReplaceNodeResults()
877 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults()
882 case ISD::UREM: { in ReplaceNodeResults()
886 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults()
891 case ISD::SDIV: { in ReplaceNodeResults()
895 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults()
900 case ISD::SREM: { in ReplaceNodeResults()
904 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults()
909 case ISD::SDIVREM: { in ReplaceNodeResults()
916 case ISD::UDIVREM: { in ReplaceNodeResults()
934 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, in vectorToVerticalVector()
953 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
969 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
980 DAG.getNode(ISD::FADD, SDLoc(Op), VT, in LowerTrig()
981 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg, in LowerTrig()
986 case ISD::FCOS: in LowerTrig()
989 case ISD::FSIN: in LowerTrig()
996 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart, in LowerTrig()
1001 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal, in LowerTrig()
1017 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSHLParts()
1018 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
1025 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
1026 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
1028 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
1029 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow); in LowerSHLParts()
1030 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
1032 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
1035 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
1036 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1038 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
1051 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; in LowerSRXParts()
1055 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSRXParts()
1056 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
1063 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
1064 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
1066 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1067 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
1068 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); in LowerSRXParts()
1070 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1071 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
1073 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1074 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
1076 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
1081 ISD::SETCC, in LowerFPTOUINT()
1085 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1148 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1149 ISD::CondCode InverseCC = in LowerSELECT_CC()
1150 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1156 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC); in LowerSELECT_CC()
1168 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1183 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1185 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
1191 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); in LowerSELECT_CC()
1192 CCSwapped = ISD::getSetCCSwappedOperands(CCInv); in LowerSELECT_CC()
1203 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1209 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
1210 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
1214 case ISD::SETONE: in LowerSELECT_CC()
1215 case ISD::SETUNE: in LowerSELECT_CC()
1216 case ISD::SETNE: in LowerSELECT_CC()
1217 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1225 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1229 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1249 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1251 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1254 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1279 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1336 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, in LowerSTORE()
1338 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr, in LowerSTORE()
1340 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1341 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1343 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift); in LowerSTORE()
1344 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift); in LowerSTORE()
1353 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src); in LowerSTORE()
1362 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
1404 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerSTORE()
1406 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, in LowerSTORE()
1413 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); in LowerSTORE()
1416 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value); in LowerSTORE()
1491 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1508 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) || in LowerLOAD()
1509 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
1521 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in LowerLOAD()
1531 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, in LowerLOAD()
1536 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)), in LowerLOAD()
1543 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1561 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) { in LowerLOAD()
1566 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, in LowerLOAD()
1572 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount); in LowerLOAD()
1573 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount); in LowerLOAD()
1602 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerLOAD()
1613 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads); in LowerLOAD()
1645 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
1654 SmallVector<ISD::InputArg, 8> LocalIns; in LowerFormalArguments()
1662 const ISD::InputArg &In = Ins[i]; in LowerFormalArguments()
1687 ISD::LoadExtType Ext = ISD::NON_EXTLOAD; in LowerFormalArguments()
1693 Ext = ISD::SEXTLOAD; in LowerFormalArguments()
1705 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1727 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in CompactSwizzlableVector()
1737 if (NewBldVec[i].getOpcode() == ISD::UNDEF) in CompactSwizzlableVector()
1752 if (NewBldVec[i].getOpcode() == ISD::UNDEF) in CompactSwizzlableVector()
1763 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), in CompactSwizzlableVector()
1769 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in ReorganizeVector()
1780 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1789 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1801 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), in ReorganizeVector()
1808 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR); in OptimizeSwizzle()
1842 case ISD::FP_ROUND: { in PerformDAGCombine()
1844 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1845 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0), in PerformDAGCombine()
1856 case ISD::FP_TO_SINT: { in PerformDAGCombine()
1858 if (FNeg.getOpcode() != ISD::FNEG) { in PerformDAGCombine()
1862 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1870 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PerformDAGCombine()
1882 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
1889 if (InVal.getOpcode() == ISD::UNDEF) in PerformDAGCombine()
1895 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
1907 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1910 } else if (InVec.getOpcode() == ISD::UNDEF) { in PerformDAGCombine()
1924 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in PerformDAGCombine()
1925 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); in PerformDAGCombine()
1930 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in PerformDAGCombine()
1935 case ISD::EXTRACT_VECTOR_ELT: { in PerformDAGCombine()
1937 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1943 if (Arg.getOpcode() == ISD::BITCAST && in PerformDAGCombine()
1944 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1947 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(), in PerformDAGCombine()
1953 case ISD::SELECT_CC: { in PerformDAGCombine()
1965 if (LHS.getOpcode() != ISD::SELECT_CC) { in PerformDAGCombine()
1972 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1982 case ISD::SETNE: return LHS; in PerformDAGCombine()
1983 case ISD::SETEQ: { in PerformDAGCombine()
1984 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()
1985 LHSCC = ISD::getSetCCInverse(LHSCC, in PerformDAGCombine()
2003 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
2022 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()