31 R600InstrInfo::R600InstrInfo(const AMDGPUSubtarget &st)  in R600InstrInfo()  function in R600InstrInfo
34 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {  in getRegisterInfo()
38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {  in isTrig()
42 bool R600InstrInfo::isVector(const MachineInstr &MI) const {  in isVector()
47 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
82 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,  in isLegalToSplitMBBAt()
93 bool R600InstrInfo::isMov(unsigned Opcode) const {  in isMov()
108 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {  in isPlaceHolderOpcode()
116 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {  in isReductionOp()
120 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {  in isCubeOp()
131 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {  in isALUInstr()
137 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {  in hasInstrModifiers()
145 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {  in isLDSInstr()
153 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {  in isLDSNoRetInstr()
157 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {  in isLDSRetInstr()
161 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {  in canBeConsideredALU()
179 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {  in isTransOnly()
185 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {  in isTransOnly()
189 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {  in isVectorOnly()
193 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {  in isVectorOnly()
197 bool R600InstrInfo::isExport(unsigned Opcode) const {  in isExport()
201 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {  in usesVertexCache()
205 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {  in usesVertexCache()
212 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {  in usesTextureCache()
216 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {  in usesTextureCache()
224 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {  in mustBeLastInClause()
234 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {  in usesAddressRegister()
238 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {  in definesAddressRegister()
242 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {  in readsLDSSrcReg()
258 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {  in getSrcIdx()
269 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {  in getSelIdx()
293 R600InstrInfo::getSrcs(MachineInstr *MI) const {  in getSrcs()
353 R600InstrInfo::ExtractSrcs(MachineInstr *MI,  in ExtractSrcs()
387         R600InstrInfo::BankSwizzle Swz) {  in Swizzle()
391   case R600InstrInfo::ALU_VEC_012_SCL_210:  in Swizzle()
393   case R600InstrInfo::ALU_VEC_021_SCL_122:  in Swizzle()
396   case R600InstrInfo::ALU_VEC_102_SCL_221:  in Swizzle()
399   case R600InstrInfo::ALU_VEC_120_SCL_212:  in Swizzle()
403   case R600InstrInfo::ALU_VEC_201:  in Swizzle()
407   case R600InstrInfo::ALU_VEC_210:  in Swizzle()
415 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {  in getTransSwizzle()
417   case R600InstrInfo::ALU_VEC_012_SCL_210: {  in getTransSwizzle()
421   case R600InstrInfo::ALU_VEC_021_SCL_122: {  in getTransSwizzle()
425   case R600InstrInfo::ALU_VEC_120_SCL_212: {  in getTransSwizzle()
429   case R600InstrInfo::ALU_VEC_102_SCL_221: {  in getTransSwizzle()
442 unsigned  R600InstrInfo::isLegalUpTo(  in isLegalUpTo()
444     const std::vector<R600InstrInfo::BankSwizzle> &Swz,  in isLegalUpTo()
446     R600InstrInfo::BankSwizzle TransSwz) const {  in isLegalUpTo()
457         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&  in isLegalUpTo()
458             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {  in isLegalUpTo()
493     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,  in NextPossibleSolution()
497   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)  in NextPossibleSolution()
500     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;  in NextPossibleSolution()
505   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;  in NextPossibleSolution()
511 bool R600InstrInfo::FindSwizzleForVectorSlot(  in FindSwizzleForVectorSlot()
513     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,  in FindSwizzleForVectorSlot()
515     R600InstrInfo::BankSwizzle TransSwz) const {  in FindSwizzleForVectorSlot()
528 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,  in isConstCompatible()
548 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,  in fitsReadPortLimitations()
563     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)  in fitsReadPortLimitations()
574   static const R600InstrInfo::BankSwizzle TransSwz[] = {  in fitsReadPortLimitations()
597 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)  in fitsConstReadLimitations()
622 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)  in fitsConstReadLimitations()
654 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {  in CreateTargetScheduleState()
693 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,  in AnalyzeBranch()
782 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,  in InsertBranch()
828 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {  in RemoveBranch()
886 R600InstrInfo::isPredicated(const MachineInstr *MI) const {  in isPredicated()
902 R600InstrInfo::isPredicable(MachineInstr *MI) const {  in isPredicable()
928 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,  in isProfitableToIfCvt()
936 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,  in isProfitableToIfCvt()
947 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,  in isProfitableToDupForIfCvt()
955 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,  in isProfitableToUnpredicate()
962 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {  in ReverseBranchCondition()
996 R600InstrInfo::DefinesPredicate(MachineInstr *MI,  in DefinesPredicate()
1003 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,  in SubsumesPredicate()
1010 R600InstrInfo::PredicateInstruction(MachineInstr *MI,  in PredicateInstruction()
1044 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {  in getPredicationCost()
1048 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
1056 bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
1079 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,  in reserveIndirectRegisters()
1100 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,  in calculateIndirectAddress()
1107 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {  in getIndirectAddrRegClass()
1111 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,  in buildIndirectWrite()
1118 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,  in buildIndirectWrite()
1143 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,  in buildIndirectRead()
1150 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,  in buildIndirectRead()
1177 unsigned R600InstrInfo::getMaxAlusPerClause() const {  in getMaxAlusPerClause()
1181 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,  in buildDefaultInstruction()
1260 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(  in buildSlotOfVectorInstruction()
1308 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,  in buildMovImm()
1318 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,  in buildMovInstr()
1324 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {  in getOperandIdx()
1328 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {  in getOperandIdx()
1332 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,  in setImmOperand()
1344 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {  in hasFlagOperand()
1348 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,  in getFlagOp()
1403 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,  in addFlag()
1424 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,  in clearFlag()