76     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))  in copyPhysReg()
154   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;  in isLDSNoRetInstr()
158   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;  in isLDSRetInstr()
266   return getOperandIdx(Opcode, OpTable[SrcNum]);  in getSrcIdx()
285     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {  in getSelIdx()
286       return getOperandIdx(Opcode, Row[1]);  in getSelIdx()
309       MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),  in getSrcs()
313         unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),  in getSrcs()
330     int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);  in getSrcs()
337           getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();  in getSrcs()
343           getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();  in getSrcs()
561     unsigned Op = getOperandIdx(IG[i]->getOpcode(),  in fitsReadPortLimitations()
1020     MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))  in PredicateInstruction()
1022     MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))  in PredicateInstruction()
1024     MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))  in PredicateInstruction()
1026     MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))  in PredicateInstruction()
1271       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));  in buildSlotOfVectorInstruction()
1273       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));  in buildSlotOfVectorInstruction()
1293   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),  in buildSlotOfVectorInstruction()
1295   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))  in buildSlotOfVectorInstruction()
1300         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));  in buildSlotOfVectorInstruction()
1324 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {  in getOperandIdx()  function in R600InstrInfo
1325   return getOperandIdx(MI.getOpcode(), Op);  in getOperandIdx()
1328 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {  in getOperandIdx()  function in R600InstrInfo
1334   int Idx = getOperandIdx(*MI, Op);  in setImmOperand()
1360       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);  in getFlagOp()
1363       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);  in getFlagOp()
1367       FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);  in getFlagOp()
1371       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;  in getFlagOp()
1372       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;  in getFlagOp()
1373       case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;  in getFlagOp()
1382       case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;  in getFlagOp()
1383       case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;  in getFlagOp()