Lines Matching refs:ISD
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
70 setOperationAction(ISD::ADD, MVT::i32, Legal); in SITargetLowering()
71 setOperationAction(ISD::ADDC, MVT::i32, Legal); in SITargetLowering()
72 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SITargetLowering()
73 setOperationAction(ISD::SUBC, MVT::i32, Legal); in SITargetLowering()
74 setOperationAction(ISD::SUBE, MVT::i32, Legal); in SITargetLowering()
76 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
77 setOperationAction(ISD::FCOS, MVT::f32, Custom); in SITargetLowering()
79 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
80 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SITargetLowering()
83 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in SITargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v8i32, Custom); in SITargetLowering()
85 setOperationAction(ISD::LOAD, MVT::v16i32, Custom); in SITargetLowering()
87 setOperationAction(ISD::STORE, MVT::v8i32, Custom); in SITargetLowering()
88 setOperationAction(ISD::STORE, MVT::v16i32, Custom); in SITargetLowering()
90 setOperationAction(ISD::STORE, MVT::i1, Custom); in SITargetLowering()
91 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in SITargetLowering()
93 setOperationAction(ISD::SELECT, MVT::i64, Custom); in SITargetLowering()
94 setOperationAction(ISD::SELECT, MVT::f64, Promote); in SITargetLowering()
95 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64); in SITargetLowering()
97 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in SITargetLowering()
98 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in SITargetLowering()
99 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in SITargetLowering()
100 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in SITargetLowering()
102 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
103 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering()
105 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in SITargetLowering()
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal); in SITargetLowering()
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); in SITargetLowering()
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); in SITargetLowering()
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in SITargetLowering()
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in SITargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); in SITargetLowering()
122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in SITargetLowering()
123 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom); in SITargetLowering()
124 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom); in SITargetLowering()
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom); in SITargetLowering()
127 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in SITargetLowering()
128 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in SITargetLowering()
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
145 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
146 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand); in SITargetLowering()
152 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand); in SITargetLowering()
156 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SITargetLowering()
163 setOperationAction(ISD::LOAD, MVT::i1, Custom); in SITargetLowering()
165 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in SITargetLowering()
166 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in SITargetLowering()
167 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in SITargetLowering()
170 setOperationAction(ISD::UDIV, MVT::i64, Expand); in SITargetLowering()
171 setOperationAction(ISD::UREM, MVT::i64, Expand); in SITargetLowering()
173 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in SITargetLowering()
174 setOperationAction(ISD::SELECT, MVT::i1, Promote); in SITargetLowering()
179 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { in SITargetLowering()
181 case ISD::LOAD: in SITargetLowering()
182 case ISD::STORE: in SITargetLowering()
183 case ISD::BUILD_VECTOR: in SITargetLowering()
184 case ISD::BITCAST: in SITargetLowering()
185 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
186 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
187 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
188 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
190 case ISD::CONCAT_VECTORS: in SITargetLowering()
201 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in SITargetLowering()
202 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in SITargetLowering()
203 setOperationAction(ISD::FRINT, MVT::f64, Legal); in SITargetLowering()
206 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in SITargetLowering()
207 setOperationAction(ISD::FDIV, MVT::f32, Custom); in SITargetLowering()
208 setOperationAction(ISD::FDIV, MVT::f64, Custom); in SITargetLowering()
210 setTargetDAGCombine(ISD::FADD); in SITargetLowering()
211 setTargetDAGCombine(ISD::FSUB); in SITargetLowering()
212 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
213 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
214 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
215 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
216 setTargetDAGCombine(ISD::AND); in SITargetLowering()
217 setTargetDAGCombine(ISD::OR); in SITargetLowering()
218 setTargetDAGCombine(ISD::UINT_TO_FP); in SITargetLowering()
222 setTargetDAGCombine(ISD::LOAD); in SITargetLowering()
223 setTargetDAGCombine(ISD::STORE); in SITargetLowering()
224 setTargetDAGCombine(ISD::ATOMIC_LOAD); in SITargetLowering()
225 setTargetDAGCombine(ISD::ATOMIC_STORE); in SITargetLowering()
226 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP); in SITargetLowering()
227 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS); in SITargetLowering()
228 setTargetDAGCombine(ISD::ATOMIC_SWAP); in SITargetLowering()
229 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD); in SITargetLowering()
230 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB); in SITargetLowering()
231 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND); in SITargetLowering()
232 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR); in SITargetLowering()
233 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR); in SITargetLowering()
234 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND); in SITargetLowering()
235 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN); in SITargetLowering()
236 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX); in SITargetLowering()
237 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN); in SITargetLowering()
238 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX); in SITargetLowering()
386 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr, in LowerParameter()
391 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, in LowerParameter()
401 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, in LowerFormalArguments()
412 SmallVector<ISD::InputArg, 16> Splits; in LowerFormalArguments()
416 const ISD::InputArg &Arg = Ins[i]; in LowerFormalArguments()
436 ISD::InputArg NewArg = Arg; in LowerFormalArguments()
507 const ISD::InputArg &Arg = Ins[i]; in LowerFormalArguments()
532 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
576 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); in LowerFormalArguments()
685 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); in LowerOperation()
686 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
687 case ISD::LOAD: { in LowerOperation()
695 case ISD::FSIN: in LowerOperation()
696 case ISD::FCOS: in LowerOperation()
698 case ISD::SELECT: return LowerSELECT(Op, DAG); in LowerOperation()
699 case ISD::FDIV: return LowerFDIV(Op, DAG); in LowerOperation()
700 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
701 case ISD::GlobalAddress: { in LowerOperation()
706 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
707 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
747 if (Intr->getOpcode() == ISD::SETCC) { in LowerBRCOND()
752 ISD::SETNE); in LowerBRCOND()
757 BR = findUser(BRCOND, ISD::BR); in LowerBRCOND()
761 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN); in LowerBRCOND()
774 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL, in LowerBRCOND()
783 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops); in LowerBRCOND()
792 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg); in LowerBRCOND()
828 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr, in LowerGlobalAddress()
830 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr, in LowerGlobalAddress()
833 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue), in LowerGlobalAddress()
835 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue), in LowerGlobalAddress()
838 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in LowerGlobalAddress()
932 return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
933 DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1))); in LowerINTRINSIC_WO_CHAIN()
1024 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1)); in LowerSELECT()
1025 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2)); in LowerSELECT()
1027 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero); in LowerSELECT()
1028 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero); in LowerSELECT()
1032 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One); in LowerSELECT()
1033 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT()
1037 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi); in LowerSELECT()
1038 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res); in LowerSELECT()
1062 if (RHS.getOpcode() == ISD::FSQRT) in LowerFastFDIV()
1074 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip); in LowerFastFDIV()
1094 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in LowerFDIV32()
1106 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT); in LowerFDIV32()
1108 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One); in LowerFDIV32()
1110 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3); in LowerFDIV32()
1114 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); in LowerFDIV32()
1116 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); in LowerFDIV32()
1133 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
1137 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
1139 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
1141 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
1145 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
1146 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
1148 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64, in LowerFDIV64()
1160 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); in LowerFDIV64()
1161 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y); in LowerFDIV64()
1162 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0); in LowerFDIV64()
1163 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64()
1165 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi); in LowerFDIV64()
1166 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi); in LowerFDIV64()
1169 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi); in LowerFDIV64()
1171 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi); in LowerFDIV64()
1173 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ); in LowerFDIV64()
1174 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ); in LowerFDIV64()
1175 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen); in LowerFDIV64()
1229 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg, in LowerTrig()
1233 case ISD::FCOS: in LowerTrig()
1235 case ISD::FSIN: in LowerTrig()
1291 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) { in performUCharToFloatCombine()
1310 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT, in performUCharToFloatCombine()
1343 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops); in performUCharToFloatCombine()
1398 if (N0.getOpcode() != ISD::ADD) in performSHLPtrCombine()
1419 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); in performSHLPtrCombine()
1422 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset); in performSHLPtrCombine()
1437 if (LHS.getOpcode() == ISD::SETCC && in performAndCombine()
1438 RHS.getOpcode() == ISD::SETCC) { in performAndCombine()
1439 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get(); in performAndCombine()
1440 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get(); in performAndCombine()
1444 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X) in performAndCombine()
1447 if (LCC == ISD::SETO) { in performAndCombine()
1451 if (RCC == ISD::SETUNE) { in performAndCombine()
1523 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
1529 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
1590 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in performSetCCCombine()
1591 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) { in performSetCCCombine()
1615 case ISD::SETCC: in PerformDAGCombine()
1617 case ISD::FMAXNUM: // TODO: What about fmax_legacy? in PerformDAGCombine()
1618 case ISD::FMINNUM: in PerformDAGCombine()
1651 case ISD::UINT_TO_FP: { in PerformDAGCombine()
1654 case ISD::FADD: { in PerformDAGCombine()
1674 if (LHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1678 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS); in PerformDAGCombine()
1683 if (RHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1687 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS); in PerformDAGCombine()
1693 case ISD::FSUB: { in PerformDAGCombine()
1708 if (LHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1714 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS); in PerformDAGCombine()
1716 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS); in PerformDAGCombine()
1720 if (RHS.getOpcode() == ISD::FADD) { in PerformDAGCombine()
1726 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS); in PerformDAGCombine()
1736 case ISD::LOAD: in PerformDAGCombine()
1737 case ISD::STORE: in PerformDAGCombine()
1738 case ISD::ATOMIC_LOAD: in PerformDAGCombine()
1739 case ISD::ATOMIC_STORE: in PerformDAGCombine()
1740 case ISD::ATOMIC_CMP_SWAP: in PerformDAGCombine()
1741 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: in PerformDAGCombine()
1742 case ISD::ATOMIC_SWAP: in PerformDAGCombine()
1743 case ISD::ATOMIC_LOAD_ADD: in PerformDAGCombine()
1744 case ISD::ATOMIC_LOAD_SUB: in PerformDAGCombine()
1745 case ISD::ATOMIC_LOAD_AND: in PerformDAGCombine()
1746 case ISD::ATOMIC_LOAD_OR: in PerformDAGCombine()
1747 case ISD::ATOMIC_LOAD_XOR: in PerformDAGCombine()
1748 case ISD::ATOMIC_LOAD_NAND: in PerformDAGCombine()
1749 case ISD::ATOMIC_LOAD_MIN: in PerformDAGCombine()
1750 case ISD::ATOMIC_LOAD_MAX: in PerformDAGCombine()
1751 case ISD::ATOMIC_LOAD_UMIN: in PerformDAGCombine()
1752 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics. in PerformDAGCombine()
1761 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) { in PerformDAGCombine()
1766 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr; in PerformDAGCombine()
1772 case ISD::AND: in PerformDAGCombine()
1774 case ISD::OR: in PerformDAGCombine()