38 SITargetLowering::SITargetLowering(TargetMachine &TM,  in SITargetLowering()  function in SITargetLowering
247 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,  in isShuffleMaskLegal()
265 bool SITargetLowering::isLegalAddressingMode(const AddrMode &AM,  in isLegalAddressingMode()
297 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,  in allowsMisalignedMemoryAccesses()
336 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,  in getOptimalMemOpType()
357 SITargetLowering::getPreferredVectorAction(EVT VT) const {  in getPreferredVectorAction()
364 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
371 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,  in LowerParameter()
399 SDValue SITargetLowering::LowerFormalArguments(  in LowerFormalArguments()
591 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(  in EmitInstrWithCustomInserter()
619 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {  in enableAggressiveFMAFusion()
630 EVT SITargetLowering::getSetCCResultType(LLVMContext &Ctx, EVT VT) const {  in getSetCCResultType()
637 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {  in getScalarShiftAmountTy()
656 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {  in isFMAFasterThanFMulAndFAdd()
682 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {  in LowerOperation()
728 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {  in LowerFrameIndex()
738 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,  in LowerBRCOND()
813 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,  in LowerGlobalAddress()
841 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
940 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,  in LowerINTRINSIC_VOID()
980 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {  in LowerLOAD()
1005 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,  in LowerSampleIntrinsic()
1014 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT()
1043 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFastFDIV()
1080 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV32()
1119 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV64()
1186 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV()
1198 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {  in LowerSTORE()
1225 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {  in LowerTrig()
1246 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,  in performUCharToFloatCombine()
1392 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,  in performSHLPtrCombine()
1425 SDValue SITargetLowering::performAndCombine(SDNode *N,  in performAndCombine()
1478 SDValue SITargetLowering::performOrCombine(SDNode *N,  in performOrCombine()
1507 SDValue SITargetLowering::performClassCombine(SDNode *N,  in performClassCombine()
1540 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,  in performMin3Max3Combine()
1576 SDValue SITargetLowering::performSetCCCombine(SDNode *N,  in performSetCCCombine()
1607 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
1786 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {  in analyzeImmediate()
1824 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,  in adjustWritemask()
1905 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,  in legalizeTargetIndependentNode()
1925 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,  in PostISelFolding()
1943 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,  in AdjustInstrPostInstrSelection()
1989 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,  in wrapAddr64Rsrc()
2040 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,  in buildRSRC()
2071 MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,  in buildScratchRSRC()
2082 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
2096 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,  in getRegForInlineAsmConstraint()