Lines Matching refs:RegState
425 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
504 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in storeRegToStackSlot()
505 .addReg(AMDGPU::SGPR0, RegState::Undef); in storeRegToStackSlot()
551 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in loadRegFromStackSlot()
552 .addReg(AMDGPU::SGPR0, RegState::Undef); in loadRegFromStackSlot()
688 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit); in expandPostRAPseudo()
692 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit) in expandPostRAPseudo()
693 .addReg(AMDGPU::SCC, RegState::Implicit); in expandPostRAPseudo()
714 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
717 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
722 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
725 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
1849 .addReg(AMDGPU::VCC, RegState::ImplicitDefine); in legalizeOperands()
1856 .addReg(AMDGPU::VCC, RegState::ImplicitDefine) in legalizeOperands()
1857 .addReg(AMDGPU::VCC, RegState::Implicit); in legalizeOperands()
2637 .addReg(IndirectBaseReg, RegState::Define) in buildIndirectWrite()