30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)  in SIInstrInfo()  function in SIInstrInfo
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
189 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,  in getLdStBaseRegImmOfs()
276 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,  in shouldClusterLoads()
299 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
429 unsigned SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {  in commuteOpcode()
449 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
461 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
515 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
563 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,  in calculateLDSSpillAddress()
657 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,  in insertNOPs()
671 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
754 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,  in commuteInstruction()
830 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,  in findCommutedOpIndices()
865 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,  in buildMovInstr()
873 bool SIInstrInfo::isMov(unsigned Opcode) const {  in isMov()
885 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {  in isSafeToMoveRegClassDefs()
903 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,  in FoldImmediate()
1015 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,  in isTriviallyReMaterializable()
1034 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,  in checkInstOffsetsDoNotOverlap()
1054 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,  in areMemAccessesTriviallyDisjoint()
1108 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
1147 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
1163 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,  in isLiteralConstant()
1183 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,  in isImmOperandLegal()
1202 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
1210 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
1218 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
1224 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
1256 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,  in verifyInstruction()
1375 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {  in getVALUOp()
1432 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {  in isSALUOpSupportedOnVALU()
1436 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
1453 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {  in canReadVGPR()
1465 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {  in legalizeOpWithMove()
1492 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,  in buildExtractSubReg()
1520 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
1542 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,  in split64BitImm()
1573 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {  in swapOperands()
1580 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,  in isOperandLegal()
1633 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {  in legalizeOperands()
1906 void SIInstrInfo::splitSMRD(MachineInstr *MI,  in splitSMRD()
2000 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {  in moveSMRDToVALU()
2104 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {  in moveToVALU()
2314 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,  in calculateIndirectAddress()
2320 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {  in getIndirectAddrRegClass()
2324 void SIInstrInfo::splitScalar64BitUnaryOp(  in splitScalar64BitUnaryOp()
2376 void SIInstrInfo::splitScalar64BitBinaryOp(  in splitScalar64BitBinaryOp()
2440 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,  in splitScalar64BitBCNT()
2480 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,  in splitScalar64BitBFE()
2541 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,  in addDescImplicitUseDef()
2559 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,  in findUsedSGPR()
2627 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(  in buildIndirectWrite()
2645 MachineInstrBuilder SIInstrInfo::buildIndirectRead(  in buildIndirectRead()
2663 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,  in reserveIndirectRegisters()
2691 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
2700 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()