1782     MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);  in legalizeOperands()  local
1784     if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),  in legalizeOperands()
1795     unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,  in legalizeOperands()
1799     unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,  in legalizeOperands()
1874                   .addOperand(*SRsrc)  in legalizeOperands()
1887       SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);  in legalizeOperands()
1902     SRsrc->setReg(NewSRsrc);  in legalizeOperands()
2038       unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);  in moveSMRDToVALU()  local
2051       BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)  in moveSMRDToVALU()
2062         MI->getOperand(2).setReg(SRsrc);  in moveSMRDToVALU()
2064         MI->getOperand(2).ChangeToRegister(SRsrc, false);  in moveSMRDToVALU()