735     unsigned Src0 = MI->getOperand(1).getReg();  in expandPostRAPseudo()  local
740         .addReg(RI.getSubReg(Src0, AMDGPU::sub0))  in expandPostRAPseudo()
744         .addReg(RI.getSubReg(Src0, AMDGPU::sub1))  in expandPostRAPseudo()
764   MachineOperand &Src0 = MI->getOperand(Src0Idx);  in commuteInstruction()  local
765   if (!Src0.isReg())  in commuteInstruction()
778        !isOperandLegal(MI, Src1Idx, &Src0))) {  in commuteInstruction()
808     unsigned Reg = Src0.getReg();  in commuteInstruction()
809     unsigned SubReg = Src0.getSubReg();  in commuteInstruction()
811       Src0.ChangeToImmediate(Src1.getImm());  in commuteInstruction()
918     MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);  in FoldImmediate()  local
924     if (Src0->isReg() && Src0->getReg() == Reg) {  in FoldImmediate()
957       Src0->setReg(Src1Reg);  in FoldImmediate()
958       Src0->setSubReg(Src1SubReg);  in FoldImmediate()
978       if (!Src0->isImm() &&  in FoldImmediate()
979           (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))  in FoldImmediate()
1360     const MachineOperand &Src0 = MI->getOperand(Src0Idx);  in verifyInstruction()  local
1363     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {  in verifyInstruction()
1364       if (!compareMachineOp(Src0, Src1) &&  in verifyInstruction()
1365           !compareMachineOp(Src0, Src2)) {  in verifyInstruction()
1762     unsigned Src0 = MI->getOperand(1).getReg();  in legalizeOperands()  local
1764     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);  in legalizeOperands()
1769               .addReg(Src0);  in legalizeOperands()
2332   MachineOperand &Src0 = Inst->getOperand(1);  in splitScalar64BitUnaryOp()  local
2338   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitUnaryOp()
2339     MRI.getRegClass(Src0.getReg()) :  in splitScalar64BitUnaryOp()
2344   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitUnaryOp()
2354   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitUnaryOp()
2384   MachineOperand &Src0 = Inst->getOperand(1);  in splitScalar64BitBinaryOp()  local
2391   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitBinaryOp()
2392     MRI.getRegClass(Src0.getReg()) :  in splitScalar64BitBinaryOp()
2402   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitBinaryOp()
2415   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitBinaryOp()