Lines Matching refs:addReg
339 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
352 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
360 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
382 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
422 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc)); in copyPhysReg()
425 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
500 .addReg(SrcReg) in storeRegToStackSlot()
504 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in storeRegToStackSlot()
505 .addReg(AMDGPU::SGPR0, RegState::Undef); in storeRegToStackSlot()
511 .addReg(SrcReg); in storeRegToStackSlot()
551 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in loadRegFromStackSlot()
552 .addReg(AMDGPU::SGPR0, RegState::Undef); in loadRegFromStackSlot()
605 .addReg(InputPtrReg) in calculateLDSSpillAddress()
608 .addReg(InputPtrReg) in calculateLDSSpillAddress()
613 .addReg(STmp1) in calculateLDSSpillAddress()
614 .addReg(STmp0); in calculateLDSSpillAddress()
617 .addReg(STmp1) in calculateLDSSpillAddress()
618 .addReg(TIDIGXReg); in calculateLDSSpillAddress()
621 .addReg(STmp0) in calculateLDSSpillAddress()
622 .addReg(TIDIGYReg) in calculateLDSSpillAddress()
623 .addReg(TIDReg); in calculateLDSSpillAddress()
626 .addReg(TIDReg) in calculateLDSSpillAddress()
627 .addReg(TIDIGZReg); in calculateLDSSpillAddress()
638 .addReg(TIDReg); in calculateLDSSpillAddress()
644 .addReg(TIDReg); in calculateLDSSpillAddress()
652 .addReg(TIDReg); in calculateLDSSpillAddress()
686 .addReg(RegLo) in expandPostRAPseudo()
688 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit); in expandPostRAPseudo()
690 .addReg(RegHi) in expandPostRAPseudo()
692 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit) in expandPostRAPseudo()
693 .addReg(AMDGPU::SCC, RegState::Implicit); in expandPostRAPseudo()
714 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
717 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
721 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
722 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
724 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
725 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
740 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo()
741 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) in expandPostRAPseudo()
744 .addReg(RI.getSubReg(Src0, AMDGPU::sub1)) in expandPostRAPseudo()
745 .addReg(RI.getSubReg(Src1, AMDGPU::sub1)) in expandPostRAPseudo()
870 DstReg) .addReg(SrcReg); in buildMovInstr()
1512 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
1515 .addReg(NewSuperReg, 0, SubIdx); in buildExtractSubReg()
1561 .addReg(LoDst) in split64BitImm()
1563 .addReg(HiDst) in split64BitImm()
1769 .addReg(Src0); in legalizeOperands()
1827 .addReg(Zero64) in legalizeOperands()
1829 .addReg(SRsrcFormatLo) in legalizeOperands()
1831 .addReg(SRsrcFormatHi) in legalizeOperands()
1847 .addReg(SRsrcPtrLo) in legalizeOperands()
1848 .addReg(VAddr->getReg(), 0, AMDGPU::sub0) in legalizeOperands()
1849 .addReg(AMDGPU::VCC, RegState::ImplicitDefine); in legalizeOperands()
1854 .addReg(SRsrcPtrHi) in legalizeOperands()
1855 .addReg(VAddr->getReg(), 0, AMDGPU::sub1) in legalizeOperands()
1856 .addReg(AMDGPU::VCC, RegState::ImplicitDefine) in legalizeOperands()
1857 .addReg(AMDGPU::VCC, RegState::Implicit); in legalizeOperands()
1871 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr. in legalizeOperands()
1893 .addReg(NewVAddrLo) in legalizeOperands()
1895 .addReg(NewVAddrHi) in legalizeOperands()
1936 .addReg(SBase->getReg(), 0, SBase->getSubReg()) in splitSMRD()
1945 .addReg(SBase->getReg(), getKillRegState(IsKill), in splitSMRD()
1947 .addReg(OffsetSGPR); in splitSMRD()
1950 .addReg(SBase->getReg(), getKillRegState(IsKill), in splitSMRD()
1958 .addReg(SBase->getReg(), 0, SBase->getSubReg()) in splitSMRD()
1965 .addReg(SBase->getReg(), getKillRegState(IsKill), in splitSMRD()
1967 .addReg(OffsetSGPR); in splitSMRD()
1994 .addReg(RegLo) in splitSMRD()
1996 .addReg(RegHi) in splitSMRD()
2052 .addReg(DWord0) in moveSMRDToVALU()
2054 .addReg(DWord1) in moveSMRDToVALU()
2056 .addReg(DWord2) in moveSMRDToVALU()
2058 .addReg(DWord3) in moveSMRDToVALU()
2363 .addReg(DestSub0) in splitScalar64BitUnaryOp()
2365 .addReg(DestSub1) in splitScalar64BitUnaryOp()
2427 .addReg(DestSub0) in splitScalar64BitBinaryOp()
2429 .addReg(DestSub1) in splitScalar64BitBinaryOp()
2472 .addReg(MidReg); in splitScalar64BitBCNT()
2506 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0) in splitScalar64BitBFE()
2512 .addReg(MidRegLo); in splitScalar64BitBFE()
2515 .addReg(MidRegLo) in splitScalar64BitBFE()
2517 .addReg(MidRegHi) in splitScalar64BitBFE()
2530 .addReg(Src.getReg(), 0, AMDGPU::sub0); in splitScalar64BitBFE()
2533 .addReg(Src.getReg(), 0, AMDGPU::sub0) in splitScalar64BitBFE()
2535 .addReg(TmpReg) in splitScalar64BitBFE()
2637 .addReg(IndirectBaseReg, RegState::Define) in buildIndirectWrite()
2639 .addReg(IndirectBaseReg) in buildIndirectWrite()
2640 .addReg(OffsetReg) in buildIndirectWrite()
2642 .addReg(ValueReg); in buildIndirectWrite()
2657 .addReg(IndirectBaseReg) in buildIndirectRead()
2658 .addReg(OffsetReg) in buildIndirectRead()