420       get(Opcode), RI.getSubReg(DestReg, SubIdx));  in copyPhysReg()
422     Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));  in copyPhysReg()
679     unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);  in expandPostRAPseudo()
680     unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);  in expandPostRAPseudo()
704     unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);  in expandPostRAPseudo()
705     unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);  in expandPostRAPseudo()
721               .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))  in expandPostRAPseudo()
724               .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))  in expandPostRAPseudo()
733     unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);  in expandPostRAPseudo()
734     unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);  in expandPostRAPseudo()
740         .addReg(RI.getSubReg(Src0, AMDGPU::sub0))  in expandPostRAPseudo()
741         .addReg(RI.getSubReg(Src1, AMDGPU::sub0))  in expandPostRAPseudo()
744         .addReg(RI.getSubReg(Src0, AMDGPU::sub1))  in expandPostRAPseudo()
745         .addReg(RI.getSubReg(Src1, AMDGPU::sub1))  in expandPostRAPseudo()
809     unsigned SubReg = Src0.getSubReg();  in commuteInstruction()
954       unsigned Src1SubReg = Src1->getSubReg();  in FoldImmediate()
956       unsigned Src2SubReg = Src2->getSubReg();  in FoldImmediate()
1512     .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());  in buildExtractSubReg()
1936                   .addReg(SBase->getReg(), 0, SBase->getSubReg())  in splitSMRD()
1946                             SBase->getSubReg())  in splitSMRD()
1951                              SBase->getSubReg())  in splitSMRD()
1958                   .addReg(SBase->getReg(), 0, SBase->getSubReg())  in splitSMRD()
1966                           SBase->getSubReg())  in splitSMRD()