719       assert(SrcOp.isReg());  in expandPostRAPseudo()
765   if (!Src0.isReg())  in commuteInstruction()
782   if (!Src1.isReg()) {  in commuteInstruction()
844   if (!MI->getOperand(Src0Idx).isReg())  in findCommutedOpIndices()
851   if (!MI->getOperand(Src1Idx).isReg())  in findCommutedOpIndices()
924     if (Src0->isReg() && Src0->getReg() == Reg) {  in FoldImmediate()
925       if (!Src1->isReg() ||  in FoldImmediate()
926           (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))  in FoldImmediate()
929       if (!Src2->isReg() ||  in FoldImmediate()
930           (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))  in FoldImmediate()
975     if (Src2->isReg() && Src2->getReg() == Reg) {  in FoldImmediate()
979           (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))  in FoldImmediate()
982       if (!Src1->isReg() ||  in FoldImmediate()
983           (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))  in FoldImmediate()
1231   if (!MO.isReg() || !MO.isUse())  in usesConstantBus()
1311     if (!MI->getOperand(i).isReg())  in verifyInstruction()
1342         if (MO.isReg()) {  in verifyInstruction()
1363     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {  in verifyInstruction()
1383     return MI.getOperand(1).isReg() ?  in getVALUOp()
1473   if (MO.isReg())  in legalizeOpWithMove()
1499   assert(SuperReg.isReg());  in buildExtractSubReg()
1593         MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;  in isOperandLegal()
1598       if (Op.isReg() && Op.getReg() != SGPRUsed &&  in isOperandLegal()
1605   if (MO->isReg()) {  in isOperandLegal()
1681       if (MO.isReg()) {  in legalizeOperands()
1710       if (!MI->getOperand(i).isReg() ||  in legalizeOperands()
1737       if (!MI->getOperand(i).isReg() ||  in legalizeOperands()
2013       if (MI->getOperand(2).isReg()) {  in moveSMRDToVALU()
2061       if (MI->getOperand(2).isReg()) {  in moveSMRDToVALU()
2128       if (Inst->getOperand(1).isReg()) {  in moveToVALU()
2236       if (Op.isReg() && Op.getReg() == AMDGPU::SCC)  in moveToVALU()
2338   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitUnaryOp()
2391   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitBinaryOp()
2396   const TargetRegisterClass *Src1RC = Src1.isReg() ?  in splitScalar64BitBinaryOp()
2452   const TargetRegisterClass *SrcRC = Src.isReg() ?  in splitScalar64BitBCNT()
2597     if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))  in findUsedSGPR()