Lines Matching refs:src0
462 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
463 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
520 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
521 opName#" $dst, $src0", pattern
525 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
526 opName#" $dst, $src0", pattern
546 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
548 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
549 opName#" $src0"> {
553 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
554 opName#" $src0"> {
561 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
562 opName#" $dst, $src0", pattern
595 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
598 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
599 opName#" $dst, $src0, $src1 [$scc]">;
602 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
603 opName#" $dst, $src0, $src1 [$scc]">;
618 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
619 opName#" $dst, $src0, $src1", pattern
623 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
624 opName#" $dst, $src0, $src1", pattern
628 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
629 opName#" $dst, $src0, $src1", pattern
634 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
635 opName#" $src0, $src1", []>;
677 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
680 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
681 opName#" $dst, $src0">;
683 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
684 opName#" $dst, $src0">;
689 (ins SReg_32:$src0, u16imm:$src1), pattern>;
701 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
839 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
840 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
853 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
857 (ins Src0RC:$src0)
862 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
867 (ins Src0RC:$src0, Src1RC:$src1)
872 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
878 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
888 string ret = "$dst, $src0"#
896 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
904 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
958 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
963 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
971 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
972 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
973 let Asm64 = "$dst, $src0, $src1, $src2";
978 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
979 field string Asm = "$dst, $src0, $vsrc1, $src2";
1009 field bits<9> src0;
1303 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1305 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1316 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1318 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1341 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1344 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1356 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1359 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1383 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1386 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1410 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1413 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1492 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1496 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1507 …(AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$sr…
1508 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1566 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1570 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1575 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1578 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1582 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1584 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1595 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1602 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1614 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1630 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1633 (Inst i32:$src0_modifiers, P.Src0VT:$src0,