Lines Matching refs:ISD
41 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
54 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_f64()
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
173 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
184 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
246 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
291 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
297 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
298 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
324 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
342 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments_32()
399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments_32()
408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
410 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
412 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
454 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
455 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments_32()
470 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; in LowerFormalArguments_32()
473 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, in LowerFormalArguments_32()
478 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); in LowerFormalArguments_32()
492 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
532 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
544 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments_64()
572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
592 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall_32()
689 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall_32()
716 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall_32()
751 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; in LowerCall_32()
762 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
765 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
768 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
771 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
780 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
797 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
813 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in LowerCall_32()
830 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
840 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
846 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
861 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
871 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
880 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
1008 ArrayRef<ISD::OutputArg> Outs) { in fixupVariableFloatArgs()
1109 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1112 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1115 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1122 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1134 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, in LowerCall_64()
1137 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, in LowerCall_64()
1161 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1168 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1170 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1188 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); in LowerCall_64()
1196 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1279 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
1291 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1298 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1302 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1311 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()
1325 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC()
1328 case ISD::SETEQ: return SPCC::ICC_E; in IntCondCCodeToICC()
1329 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1330 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
1331 case ISD::SETGT: return SPCC::ICC_G; in IntCondCCodeToICC()
1332 case ISD::SETLE: return SPCC::ICC_LE; in IntCondCCodeToICC()
1333 case ISD::SETGE: return SPCC::ICC_GE; in IntCondCCodeToICC()
1334 case ISD::SETULT: return SPCC::ICC_CS; in IntCondCCodeToICC()
1335 case ISD::SETULE: return SPCC::ICC_LEU; in IntCondCCodeToICC()
1336 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
1337 case ISD::SETUGE: return SPCC::ICC_CC; in IntCondCCodeToICC()
1343 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
1346 case ISD::SETEQ: in FPCondCCodeToFCC()
1347 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
1348 case ISD::SETNE: in FPCondCCodeToFCC()
1349 case ISD::SETUNE: return SPCC::FCC_NE; in FPCondCCodeToFCC()
1350 case ISD::SETLT: in FPCondCCodeToFCC()
1351 case ISD::SETOLT: return SPCC::FCC_L; in FPCondCCodeToFCC()
1352 case ISD::SETGT: in FPCondCCodeToFCC()
1353 case ISD::SETOGT: return SPCC::FCC_G; in FPCondCCodeToFCC()
1354 case ISD::SETLE: in FPCondCCodeToFCC()
1355 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
1356 case ISD::SETGE: in FPCondCCodeToFCC()
1357 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
1358 case ISD::SETULT: return SPCC::FCC_UL; in FPCondCCodeToFCC()
1359 case ISD::SETULE: return SPCC::FCC_ULE; in FPCondCCodeToFCC()
1360 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
1361 case ISD::SETUGE: return SPCC::FCC_UGE; in FPCondCCodeToFCC()
1362 case ISD::SETUO: return SPCC::FCC_U; in FPCondCCodeToFCC()
1363 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
1364 case ISD::SETONE: return SPCC::FCC_LG; in FPCondCCodeToFCC()
1365 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
1382 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1383 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
1388 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
1396 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); in SparcTargetLowering()
1397 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); in SparcTargetLowering()
1398 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); in SparcTargetLowering()
1399 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom); in SparcTargetLowering()
1402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1407 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1408 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1409 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1410 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1414 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1415 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1416 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1417 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1421 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1422 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1424 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1427 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1428 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1429 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1430 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1432 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1433 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1436 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1437 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1438 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1439 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1441 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1442 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1443 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1444 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1447 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1448 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1449 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1450 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1451 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1452 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1453 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1455 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1458 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1461 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1462 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1463 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1464 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1465 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1466 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1467 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1468 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1469 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1470 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1472 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1474 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); in SparcTargetLowering()
1476 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); in SparcTargetLowering()
1478 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1479 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1480 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1481 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1490 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1491 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, in SparcTargetLowering()
1495 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1499 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1502 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1503 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1505 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1510 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1511 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1514 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1515 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1516 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1517 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1518 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1519 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1520 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1521 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1522 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1523 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1524 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1525 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1526 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1527 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1528 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1529 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); in SparcTargetLowering()
1531 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1532 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); in SparcTargetLowering()
1533 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1534 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1535 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1536 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1537 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1538 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1539 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1540 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1541 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1543 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1544 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1545 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1548 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1549 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1552 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1553 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1554 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1555 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1557 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1558 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1560 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1561 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1562 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1566 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1568 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1570 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1573 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1574 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1575 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1576 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1584 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1588 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1589 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1591 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1592 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1596 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1597 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1598 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1599 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1600 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1601 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1602 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1604 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1605 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1607 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1608 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1621 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1622 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1623 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1624 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1625 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1626 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1627 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1629 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1630 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1631 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1741 ISD::CondCode CC, unsigned &SPCC) { in LookThroughSetCC()
1744 CC == ISD::SETNE && in LookThroughSetCC()
1798 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeHiLoPair()
1813 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); in makeAddress()
1834 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); in makeAddress()
1837 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); in makeAddress()
1843 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); in makeAddress()
1846 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeAddress()
1929 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
1948 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); in LowerGlobalTLSAddress()
1963 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
1965 return DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalTLSAddress()
2107 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2140 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2147 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2215 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in LowerFP_TO_SINT()
2241 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); in LowerSINT_TO_FP()
2290 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
2328 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
2371 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), in LowerVASTART()
2390 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerVAARG()
2411 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
2419 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, in LowerDYNAMIC_STACKALLOC()
2448 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2460 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2466 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2507 SDValue Ptr = DAG.getNode(ISD::ADD, in LowerRETURNADDR()
2522 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2550 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF in LowerF128Load()
2564 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Load()
2591 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
2600 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF in LowerF128Store()
2628 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Store()
2637 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
2641 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
2679 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2680 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
2682 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
2685 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2686 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
2688 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
2695 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2696 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2697 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2698 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2711 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2712 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
2713 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
2716 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2727 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
2729 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
2741 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO()
2742 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
2748 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, in LowerUMULO_SMULO()
2750 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, in LowerUMULO_SMULO()
2753 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO()
2754 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
2757 ISD::SETNE); in LowerUMULO_SMULO()
2788 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, in LowerOperation()
2790 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, in LowerOperation()
2792 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
2793 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
2794 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
2795 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
2796 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
2798 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
2800 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, in LowerOperation()
2802 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
2804 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, in LowerOperation()
2806 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()
2808 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); in LowerOperation()
2809 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
2810 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, in LowerOperation()
2813 case ISD::LOAD: return LowerF128Load(Op, DAG); in LowerOperation()
2814 case ISD::STORE: return LowerF128Store(Op, DAG); in LowerOperation()
2815 case ISD::FADD: return LowerF128Op(Op, DAG, in LowerOperation()
2817 case ISD::FSUB: return LowerF128Op(Op, DAG, in LowerOperation()
2819 case ISD::FMUL: return LowerF128Op(Op, DAG, in LowerOperation()
2821 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
2823 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
2825 case ISD::FABS: in LowerOperation()
2826 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
2827 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
2828 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
2829 case ISD::ADDC: in LowerOperation()
2830 case ISD::ADDE: in LowerOperation()
2831 case ISD::SUBC: in LowerOperation()
2832 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
2833 case ISD::UMULO: in LowerOperation()
2834 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
2835 case ISD::ATOMIC_LOAD: in LowerOperation()
2836 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); in LowerOperation()
3189 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3190 case ISD::FP_TO_UINT: in ReplaceNodeResults()
3195 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
3205 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3206 case ISD::UINT_TO_FP: in ReplaceNodeResults()
3212 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()