Lines Matching refs:IntRegs
265 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
268 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
347 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
369 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
390 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
392 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
419 defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
420 defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
421 defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
422 defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
423 defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
437 defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
438 defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
439 defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
453 (outs IntRegs:$rd), (ins i32imm:$imm22),
463 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
466 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
470 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
473 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
476 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
480 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
482 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
485 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
489 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
502 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
503 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
504 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
507 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
512 (outs IntRegs:$dst), (ins MEMri:$addr),
517 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
523 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
526 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
528 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
531 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
538 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
542 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
550 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
709 (outs IntRegs:$dst), (ins),
715 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
718 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
911 (outs IntRegs:$rd),
912 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
919 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
944 : F4_1<0b101100, (outs IntRegs:$rd),
945 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
950 : F4_2<0b101100, (outs IntRegs:$rd),
951 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
959 : F4_1<0b101100, (outs IntRegs:$rd),
960 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
964 : F4_2<0b101100, (outs IntRegs:$rd),
965 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1069 : F4_1<0b101100, (outs IntRegs:$rd),
1070 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1073 : F4_2<0b101100, (outs IntRegs:$rd),
1074 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1097 (outs IntRegs:$dst), (ins IntRegs:$src),
1112 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
1116 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
1123 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1124 IntRegs:$swap),
1140 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
1143 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,