Lines Matching refs:rd
252 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
253 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
254 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
256 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
257 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
258 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
265 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
266 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
268 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
269 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
289 (outs), (ins MEMrr:$addr, RC:$rd),
290 !strconcat(OpcStr, " $rd, [$addr]"),
291 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
293 (outs), (ins MEMri:$addr, RC:$rd),
294 !strconcat(OpcStr, " $rd, [$addr]"),
295 [(OpNode Ty:$rd, ADDRri:$addr)]>;
324 let rd = 0, rs1 = 0, rs2 = 0 in
328 let rd = 0, rs1 = 1, simm13 = 3 in
334 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
337 let rd = 0 in
400 let rd = 0, rs1 = 15 in
404 let rd = 0, rs1 = 31 in
410 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
453 (outs IntRegs:$rd), (ins i32imm:$imm22),
454 "sethi $imm22, $rd",
455 [(set i32:$rd, SETHIimm:$imm22)]>;
459 let rd = 0, imm22 = 0 in
466 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
467 "andn $rs1, $rs2, $rd",
468 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
470 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
471 "andn $rs1, $simm13, $rd", []>;
476 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
477 "orn $rs1, $rs2, $rd",
478 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
480 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
481 "orn $rs1, $simm13, $rd", []>;
485 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
486 "xnor $rs1, $rs2, $rd",
487 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
489 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
490 "xnor $rs1, $simm13, $rd", []>;
536 let Defs = [ICC], rd = 0 in {
619 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
694 let isCodeGenOnly = 1, rd = 15 in {
710 "rd %y, $dst", []>;
713 let Defs = [Y], rd = 0 in {
723 (outs FPRegs:$rd), (ins FPRegs:$rs2),
724 "fitos $rs2, $rd",
725 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
727 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
728 "fitod $rs2, $rd",
729 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
731 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
732 "fitoq $rs2, $rd",
733 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
738 (outs FPRegs:$rd), (ins FPRegs:$rs2),
739 "fstoi $rs2, $rd",
740 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
742 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
743 "fdtoi $rs2, $rd",
744 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
746 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
747 "fqtoi $rs2, $rd",
748 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
753 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
754 "fstod $rs2, $rd",
755 [(set f64:$rd, (fextend f32:$rs2))]>;
757 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
758 "fstoq $rs2, $rd",
759 [(set f128:$rd, (fextend f32:$rs2))]>,
762 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
763 "fdtos $rs2, $rd",
764 [(set f32:$rd, (fround f64:$rs2))]>;
766 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
767 "fdtoq $rs2, $rd",
768 [(set f128:$rd, (fextend f64:$rs2))]>,
771 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
772 "fqtos $rs2, $rd",
773 [(set f32:$rd, (fround f128:$rs2))]>,
776 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
777 "fqtod $rs2, $rd",
778 [(set f64:$rd, (fround f128:$rs2))]>,
783 (outs FPRegs:$rd), (ins FPRegs:$rs2),
784 "fmovs $rs2, $rd", []>;
786 (outs FPRegs:$rd), (ins FPRegs:$rs2),
787 "fnegs $rs2, $rd",
788 [(set f32:$rd, (fneg f32:$rs2))]>;
790 (outs FPRegs:$rd), (ins FPRegs:$rs2),
791 "fabss $rs2, $rd",
792 [(set f32:$rd, (fabs f32:$rs2))]>;
797 (outs FPRegs:$rd), (ins FPRegs:$rs2),
798 "fsqrts $rs2, $rd",
799 [(set f32:$rd, (fsqrt f32:$rs2))]>;
801 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
802 "fsqrtd $rs2, $rd",
803 [(set f64:$rd, (fsqrt f64:$rs2))]>;
805 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
806 "fsqrtq $rs2, $rd",
807 [(set f128:$rd, (fsqrt f128:$rs2))]>,
814 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
815 "fadds $rs1, $rs2, $rd",
816 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
818 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
819 "faddd $rs1, $rs2, $rd",
820 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
822 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
823 "faddq $rs1, $rs2, $rd",
824 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
828 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
829 "fsubs $rs1, $rs2, $rd",
830 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
832 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
833 "fsubd $rs1, $rs2, $rd",
834 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
836 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
837 "fsubq $rs1, $rs2, $rd",
838 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
844 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
845 "fmuls $rs1, $rs2, $rd",
846 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
848 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
849 "fmuld $rs1, $rs2, $rd",
850 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
852 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
853 "fmulq $rs1, $rs2, $rd",
854 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
858 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
859 "fsmuld $rs1, $rs2, $rd",
860 [(set f64:$rd, (fmul (fextend f32:$rs1),
863 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
864 "fdmulq $rs1, $rs2, $rd",
865 [(set f128:$rd, (fmul (fextend f64:$rs1),
870 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
871 "fdivs $rs1, $rs2, $rd",
872 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
874 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
875 "fdivd $rs1, $rs2, $rd",
876 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
878 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
879 "fdivq $rs1, $rs2, $rd",
880 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
890 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
911 (outs IntRegs:$rd),
913 "add $rs1, $rs2, $rd, $sym",
914 [(set i32:$rd,
940 let Predicates = [HasV9], Constraints = "$f = $rd" in {
944 : F4_1<0b101100, (outs IntRegs:$rd),
946 "mov$cond %icc, $rs2, $rd",
947 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
950 : F4_2<0b101100, (outs IntRegs:$rd),
952 "mov$cond %icc, $simm11, $rd",
953 [(set i32:$rd,
959 : F4_1<0b101100, (outs IntRegs:$rd),
961 "mov$cond %fcc0, $rs2, $rd",
962 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
964 : F4_2<0b101100, (outs IntRegs:$rd),
966 "mov$cond %fcc0, $simm11, $rd",
967 [(set i32:$rd,
973 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
975 "fmovs$cond %icc, $rs2, $rd",
976 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
978 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
980 "fmovd$cond %icc, $rs2, $rd",
981 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
983 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
985 "fmovq$cond %icc, $rs2, $rd",
986 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
992 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
994 "fmovs$cond %fcc0, $rs2, $rd",
995 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
997 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
999 "fmovd$cond %fcc0, $rs2, $rd",
1000 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1002 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1004 "fmovq$cond %fcc0, $rs2, $rd",
1005 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1014 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1015 "fmovd $rs2, $rd", []>;
1017 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1018 "fmovq $rs2, $rd", []>,
1021 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1022 "fnegd $rs2, $rd",
1023 [(set f64:$rd, (fneg f64:$rs2))]>;
1025 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1026 "fnegq $rs2, $rd",
1027 [(set f128:$rd, (fneg f128:$rs2))]>,
1030 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1031 "fabsd $rs2, $rd",
1032 [(set f64:$rd, (fabs f64:$rs2))]>;
1034 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1035 "fabsq $rs2, $rd",
1036 [(set f128:$rd, (fabs f128:$rs2))]>,
1042 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1043 "fcmps $rd, $rs1, $rs2", []>;
1045 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1046 "fcmpd $rd, $rs1, $rs2", []>;
1048 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1049 "fcmpq $rd, $rs1, $rs2", []>,
1054 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1055 "fcmpes $rd, $rs1, $rs2", []>;
1057 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1058 "fcmped $rd, $rs1, $rs2", []>;
1060 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1061 "fcmpeq $rd, $rs1, $rs2", []>,
1067 let Constraints = "$f = $rd", intcc = 0 in {
1069 : F4_1<0b101100, (outs IntRegs:$rd),
1071 "mov$cond $cc, $rs2, $rd", []>;
1073 : F4_2<0b101100, (outs IntRegs:$rd),
1075 "mov$cond $cc, $simm11, $rd", []>;
1077 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1079 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1081 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1083 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1085 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1087 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1089 } // Constraints = "$f = $rd", ...
1103 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1106 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1121 let Predicates = [HasV9], Constraints = "$swap = $rd" in
1123 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1125 "cas [$rs1], $rs2, $rd",
1126 [(set i32:$rd,