Lines Matching refs:addReg
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
88 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D); in EmitInstruction()
93 .addReg(SystemZ::R14D) in EmitInstruction()
99 .addReg(SystemZ::R14D) in EmitInstruction()
100 .addReg(MI->getOperand(0).getReg()); in EmitInstruction()
109 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D); in EmitInstruction()
114 .addReg(SystemZ::R14D) in EmitInstruction()
121 .addReg(SystemZ::R14D) in EmitInstruction()
128 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
134 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in EmitInstruction()
140 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in EmitInstruction()
191 .addImm(14).addReg(SystemZ::R0D); in EmitInstruction()
194 .addImm(15).addReg(SystemZ::R0D); in EmitInstruction()