1468                                      uint64_t Mask, uint64_t CmpVal,  in getTestUnderMaskCond()  argument
1487   if (CmpVal == 0) {  in getTestUnderMaskCond()
1493   if (EffectivelyUnsigned && CmpVal <= Low) {  in getTestUnderMaskCond()
1499   if (EffectivelyUnsigned && CmpVal < Low) {  in getTestUnderMaskCond()
1507   if (CmpVal == Mask) {  in getTestUnderMaskCond()
1513   if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {  in getTestUnderMaskCond()
1519   if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {  in getTestUnderMaskCond()
1527   if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {  in getTestUnderMaskCond()
1533   if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {  in getTestUnderMaskCond()
1543     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)  in getTestUnderMaskCond()
1545     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)  in getTestUnderMaskCond()
1547     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)  in getTestUnderMaskCond()
1549     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)  in getTestUnderMaskCond()
1564   uint64_t CmpVal = ConstOp1->getZExtValue();  in adjustForTestUnderMask()  local
1589       if (CmpVal == uint64_t(-1))  in adjustForTestUnderMask()
1591       CmpVal += 1;  in adjustForTestUnderMask()
1596     MaskVal = -(CmpVal & -CmpVal);  in adjustForTestUnderMask()
1611                                         CmpVal >> ShiftVal,  in adjustForTestUnderMask()
1620                                                CmpVal << ShiftVal,  in adjustForTestUnderMask()
1625     NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,  in adjustForTestUnderMask()
2605   SDValue CmpVal = Node->getOperand(2);  in lowerATOMIC_CMP_SWAP()  local
2628   SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,  in lowerATOMIC_CMP_SWAP()
3291   unsigned CmpVal       = MRI.createVirtualRegister(RC);  in emitAtomicCmpSwapW()  local
3331   BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)  in emitAtomicCmpSwapW()
3340     .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);  in emitAtomicCmpSwapW()