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Lines Matching refs:BaseReg

255     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
264 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
268 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
359 if (!BaseReg) { in onPlus()
360 BaseReg = TmpReg; in onPlus()
396 if (!BaseReg) { in onMinus()
397 BaseReg = TmpReg; in onMinus()
574 if (!BaseReg) { in onRBrac()
575 BaseReg = TmpReg; in onRBrac()
681 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
799 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexReg() argument
804 if (BaseReg != 0 && IndexReg != 0) { in CheckBaseRegAndIndexReg()
805 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) && in CheckBaseRegAndIndexReg()
812 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) && in CheckBaseRegAndIndexReg()
819 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) { in CheckBaseRegAndIndexReg()
825 if (((BaseReg == X86::BX || BaseReg == X86::BP) && in CheckBaseRegAndIndexReg()
827 ((BaseReg == X86::SI || BaseReg == X86::DI) && in CheckBaseRegAndIndexReg()
845 unsigned diReg = Op1.Mem.BaseReg; in doSrcDstMatch()
846 unsigned siReg = Op2.Mem.BaseReg; in doSrcDstMatch()
1013 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm() argument
1050 BaseReg = BaseReg ? BaseReg : 1; in CreateMemForInlineAsm()
1051 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg, in CreateMemForInlineAsm()
1287 int BaseReg = SM.getBaseReg(); in ParseIntelBracExpression() local
1292 if (!BaseReg && !IndexReg) { in ParseIntelBracExpression()
1299 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) { in ParseIntelBracExpression()
1303 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg, in ParseIntelBracExpression()
1308 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start, in ParseIntelBracExpression()
1886 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
1892 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr; in ParseMemOperand()
1893 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) { in ParseMemOperand()
1934 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) && in ParseMemOperand()
1972 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) && in ParseMemOperand()
1973 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP && in ParseMemOperand()
1974 BaseReg != X86::SI && BaseReg != X86::DI)) && in ParseMemOperand()
1975 BaseReg != X86::DX) { in ParseMemOperand()
1979 if (BaseReg == 0 && in ParseMemOperand()
1986 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) { in ParseMemOperand()
1991 if (SegReg || BaseReg || IndexReg) in ParseMemOperand()
1992 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg, in ParseMemOperand()
2173 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) { in ParseInstruction()
2175 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); in ParseInstruction()
2185 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) { in ParseInstruction()
2187 Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); in ParseInstruction()