255     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
264       State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),  in IntelExprStateMachine()
269     unsigned getIndexReg() { return IndexReg; }  in getIndexReg()
362             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onPlus()
363             IndexReg = TmpReg;  in onPlus()
399             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onMinus()
400             IndexReg = TmpReg;  in onMinus()
436           assert (!IndexReg && "IndexReg already set!");  in onRegister()
438           IndexReg = Reg;  in onRegister()
485           assert (!IndexReg && "IndexReg already set!");  in onInteger()
486           IndexReg = TmpReg;  in onInteger()
577             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onRBrac()
578             IndexReg = TmpReg;  in onRBrac()
682                         unsigned IndexReg, unsigned Scale, SMLoc Start,
799 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexReg()  argument
804   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexReg()
806         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexReg()
807          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&  in CheckBaseRegAndIndexReg()
808         IndexReg != X86::RIZ) {  in CheckBaseRegAndIndexReg()
813         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexReg()
814          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&  in CheckBaseRegAndIndexReg()
815         IndexReg != X86::EIZ){  in CheckBaseRegAndIndexReg()
820       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexReg()
821           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexReg()
826            IndexReg != X86::SI && IndexReg != X86::DI) ||  in CheckBaseRegAndIndexReg()
828            IndexReg != X86::BX && IndexReg != X86::BP)) {  in CheckBaseRegAndIndexReg()
1013     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForInlineAsm()  argument
1052                                IndexReg, Scale, Start, End, Size, Identifier,  in CreateMemForInlineAsm()
1288   int IndexReg = SM.getIndexReg();  in ParseIntelBracExpression()  local
1292     if (!BaseReg && !IndexReg) {  in ParseIntelBracExpression()
1299     if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {  in ParseIntelBracExpression()
1304                                  IndexReg, Scale, Start, End, Size);  in ParseIntelBracExpression()
1308   return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,  in ParseIntelBracExpression()
1886   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
1912       if (ParseRegister(IndexReg, L, L)) return nullptr;  in ParseMemOperand()
1980       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in ParseMemOperand()
1986   if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {  in ParseMemOperand()
1991   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
1993                                  IndexReg, Scale, MemStart, MemEnd);  in ParseMemOperand()
2173         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {  in ParseInstruction()
2185         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {  in ParseInstruction()