174 static void translateRegister(MCInst &mcInst, Reg reg) {  in translateRegister()  argument
183   mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));  in translateRegister()
240 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {  in translateSrcIndex()  argument
252   mcInst.addOperand(baseReg);  in translateSrcIndex()
256   mcInst.addOperand(segmentReg);  in translateSrcIndex()
265 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {  in translateDstIndex()  argument
277   mcInst.addOperand(baseReg);  in translateDstIndex()
287 static void translateImmediate(MCInst &mcInst, uint64_t immediate,  in translateImmediate()  argument
345       switch (mcInst.getOpcode()) {  in translateImmediate()
373       mcInst.setOpcode(NewOpc);  in translateImmediate()
379       switch (mcInst.getOpcode()) {  in translateImmediate()
405       mcInst.setOpcode(NewOpc);  in translateImmediate()
410       switch (mcInst.getOpcode()) {  in translateImmediate()
534       mcInst.setOpcode(NewOpc);  in translateImmediate()
542     mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));  in translateImmediate()
545     mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));  in translateImmediate()
548     mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));  in translateImmediate()
570                                mcInst, Dis))  in translateImmediate()
571     mcInst.addOperand(MCOperand::CreateImm(immediate));  in translateImmediate()
577     mcInst.addOperand(segmentReg);  in translateImmediate()
587 static bool translateRMRegister(MCInst &mcInst,  in translateRMRegister()  argument
609     mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;  in translateRMRegister()
625 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,  in translateRMMemory()  argument
668     uint32_t Opcode = mcInst.getOpcode();  in translateRMMemory()
789   mcInst.addOperand(baseReg);  in translateRMMemory()
790   mcInst.addOperand(scaleAmount);  in translateRMMemory()
791   mcInst.addOperand(indexReg);  in translateRMMemory()
794                                insn.displacementSize, mcInst, Dis))  in translateRMMemory()
795     mcInst.addOperand(displacement);  in translateRMMemory()
796   mcInst.addOperand(segmentReg);  in translateRMMemory()
808 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,  in translateRM()  argument
831     return translateRMRegister(mcInst, insn);  in translateRM()
848     return translateRMMemory(mcInst, insn, Dis);  in translateRM()
857 static void translateFPRegister(MCInst &mcInst,  in translateFPRegister()  argument
859   mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));  in translateFPRegister()
868 static bool translateMaskRegister(MCInst &mcInst,  in translateMaskRegister()  argument
875   mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));  in translateMaskRegister()
886 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,  in translateOperand()  argument
894     translateRegister(mcInst, insn.reg);  in translateOperand()
897     return translateMaskRegister(mcInst, insn.writemask);  in translateOperand()
899     return translateRM(mcInst, operand, insn, Dis);  in translateOperand()
914     translateImmediate(mcInst,  in translateOperand()
921     return translateSrcIndex(mcInst, insn);  in translateOperand()
923     return translateDstIndex(mcInst, insn);  in translateOperand()
929     translateRegister(mcInst, insn.opcodeRegister);  in translateOperand()
932     translateFPRegister(mcInst, insn.modRM & 7);  in translateOperand()
935     translateRegister(mcInst, insn.vvvv);  in translateOperand()
938     return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],  in translateOperand()
949 static bool translateInstruction(MCInst &mcInst,  in translateInstruction()  argument
957   mcInst.setOpcode(insn.instructionID);  in translateInstruction()
962     if(mcInst.getOpcode() == X86::REP_PREFIX)  in translateInstruction()
963       mcInst.setOpcode(X86::XRELEASE_PREFIX);  in translateInstruction()
964     else if(mcInst.getOpcode() == X86::REPNE_PREFIX)  in translateInstruction()
965       mcInst.setOpcode(X86::XACQUIRE_PREFIX);  in translateInstruction()
972       if (translateOperand(mcInst, Op, insn, Dis)) {  in translateInstruction()